diff options
| author | Johan Hovold <johan+linaro@kernel.org> | 2022-07-05 13:40:31 +0200 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-07-06 21:39:48 -0500 |
| commit | 3a5da59af38d77088aa5226208cca0beb9125485 (patch) | |
| tree | 9497c8c9286a6050c6862a5a35cc211611f21f8d /arch/arm64/boot/dts/qcom | |
| parent | e30d9f1e58c0f860b8a740c63527106146f0f3fd (diff) | |
arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs
Clean up the PCIe PHY nodes by using a non-empty ranges property.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220705114032.22787-14-johan+linaro@kernel.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8996.dtsi | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 21371cd9cb1b..97401e5f5326 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -593,7 +593,7 @@ reg = <0x00034000 0x488>; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x00034000 0x4000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, @@ -606,10 +606,10 @@ reset-names = "phy", "common", "cfg"; status = "disabled"; - pciephy_0: phy@35000 { - reg = <0x00035000 0x130>, - <0x00035200 0x200>, - <0x00035400 0x1dc>; + pciephy_0: phy@1000 { + reg = <0x1000 0x130>, + <0x1200 0x200>, + <0x1400 0x1dc>; #phy-cells = <0>; #clock-cells = <0>; @@ -620,10 +620,10 @@ reset-names = "lane0"; }; - pciephy_1: phy@36000 { - reg = <0x00036000 0x130>, - <0x00036200 0x200>, - <0x00036400 0x1dc>; + pciephy_1: phy@2000 { + reg = <0x2000 0x130>, + <0x2200 0x200>, + <0x2400 0x1dc>; #phy-cells = <0>; #clock-cells = <0>; @@ -634,10 +634,10 @@ reset-names = "lane1"; }; - pciephy_2: phy@37000 { - reg = <0x00037000 0x130>, - <0x00037200 0x200>, - <0x00037400 0x1dc>; + pciephy_2: phy@3000 { + reg = <0x3000 0x130>, + <0x3200 0x200>, + <0x3400 0x1dc>; #phy-cells = <0>; #clock-cells = <0>; |