diff options
| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2019-06-14 12:53:33 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-07-29 15:36:00 +0200 |
| commit | 5b971c71dd64c08c73c37f754f60a7d777ea70e9 (patch) | |
| tree | cb6b2b99afe6ac8210a6819f92abe9617455a126 /arch/arm64/boot/dts/renesas/r8a774a1.dtsi | |
| parent | 0a930f64a1cc36a34797a9e54f3040ad1d5833f2 (diff) | |
arm64: dts: renesas: r8a774a1: Add CANFD support
Add CANFD support to the SoC specific dtsi.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774a1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 0ef8f5326b64..a849ca726a51 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1151,6 +1151,31 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a774a1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774A1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; |