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authorDien Pham <dien.pham.ry@renesas.com>2018-01-29 19:21:20 +0100
committerSimon Horman <horms+renesas@verge.net.au>2018-03-13 19:05:26 +0100
commitfbdad84cc759abc469e476ee2518d77280e80cd0 (patch)
treed4fcc25231032a16f90f1d9b6dbf66ee7700f439 /arch/arm64/boot/dts/renesas/r8a7796.dtsi
parent8091788f3d3856a0b6eabebf4e34cfecb38cfe96 (diff)
arm64: dts: renesas: r8a7796: Update OPPs to support CA53 dfs
Describe frequencies, other than the default for CA53 cores. This is a pre-requisite for using providing alternative frequencies for use with CPUFreq with these cores. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 157bd28014ed..076a9c9346ae 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -204,11 +204,27 @@
compatible = "operating-points-v2";
opp-shared;
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
};
/* External PCIe clock - can be overridden by the board */