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authorArnd Bergmann <arnd@arndb.de>2017-10-30 14:26:01 +0100
committerArnd Bergmann <arnd@arndb.de>2017-10-30 14:26:01 +0100
commit918c822374431a2555c8a4f6e29ab1f93e556742 (patch)
treec960d507643fcd113c1852fdaf5235d2d33452c0 /arch/arm64/boot/dts/renesas/r8a77970.dtsi
parent11c3889c237b8ff4ff62420d9a964b10e15f330d (diff)
parente9ce35386b215d3f5d0fbab3cc24b69b8d57d7e6 (diff)
Merge tag 'renesas-arm64-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Second Round of Renesas ARM64 Based SoC DT Updates for v4.15" from Simon Horman: * r8a7795 (H3) and r8a7796 (M3-W) SoCs - Use R-Car Gen 3 fallback compat string for GPIO Simon Horman says "Use newly added R-Car GPIO Gen 1, 2 and 3 fallback compat strings in peace of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of Renesas ARM and arm64 based SoCs. * r8a7795 (H3) and r8a7796 (M3-W) Salvator boards - Add dr_mode property for USB2.0 channel 0 Shimoda-san says "Since Salvator-X[S] have a USB2.0 dual-role channel (CN9), this patch adds dr_mode property for USB2.0 channel 0 (EHCI/OHCI and HS-USB) as "otg". Using dual-role channel (or not) is related to the type of USB receptor on board specification. So, I added the property into the salvator-common.dtsi." - Add pfc node for USB3.0 channel 0 Shimoda-san says "Since a R-Car Gen3 bootloader enables the PFC of USB3.0 channel 0, the USB3.0 host controller works without this setting on the kernel. But, this setting should have salvator-common.dtsi. So, this patch adds the pfc node for USB3.0 channel 0." * r8a7795 (H3) and r8a7796 (M3-W) Salvator and ULCB boards - Correct audio_clkout Morimoto-san says ""audio_clkout" is dummy clock of <&rcar_sound 0> to avoid clock loop which invites probe conflct. Thus <&rcar_sound 0> and "audio_clkout" should be same value." * r8a7795 (H3) and r8a7796 (M3-W) Salvator and ULCB, and r8a77995 (D3) Draak boards - Drop "avb_phy_int" from avb_pins Shimoda-san says "Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling and it will be handled by a phy driver as a gpio pin, this patch removes the "avb_phy_int" from the avb_pins node." * r8a77995 (D3) Draak board - Enable PWM channels Shimoda-san says "Each channel connects to LTC2644 for brightness control." * r8a77970 (V3M) Eagle and ULCB Kingfisher boards - Add initial device tree support * tag 'renesas-arm64-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits) arm64: dts: renesas: salvator-common: add dr_mode property for USB2.0 channel 0 arm64: dts: r8a7796: Use R-Car GPIO Gen3 fallback compat string arm64: dts: r8a7795: Use R-Car GPIO Gen3 fallback compat string arm64: renesas: ulcb: fixup audio_clkout arm64: renesas: salvator-common: fixup audio_clkout arm64: dts: renesas: eagle: add EtherAVB support arm64: dts: r8a77995: Add INTC-EX device node arm64: dts: r8a77970: Add INTC-EX device node arm64: dts: r8a7796: Add INTC-EX device node arm64: dts: ulcb-kf: hog USB3 hub control gpios arm64: dts: ulcb-kf: enable PCA9548 on I2C4 arm64: dts: ulcb-kf: enable PCA9548 on I2C2 arm64: dts: ulcb-kf: enable TCA9539 on I2C4 arm64: dts: ulcb-kf: enable TCA9539 on I2C2 arm64: dts: ulcb-kf: enable USB3.0 Host arm64: dts: ulcb-kf: enable PCIE0/1 arm64: dts: ulcb-kf: enable USB2.0 Host channel 0 arm64: dts: ulcb-kf: enable HSUSB arm64: dts: ulcb-kf: enable CAN0/1 arm64: dts: ulcb-kf: enable SCIF1 ...
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a77970.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index aa9032d34189..97e6981938e7 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -124,6 +124,22 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 407>;
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;