diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-01-21 12:00:06 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-01-25 10:32:43 +0100 |
| commit | 9e921faa305369e5cbe4fd8f3212a1ad6aa85c79 (patch) | |
| tree | 3070665c36c0954b9e6323d2a5da25d057860bb1 /arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | |
| parent | bff4e5dac9992ba5a6b2d318570b993f4c616b5c (diff) | |
arm64: dts: renesas: falcon: Complete SCIF0 nodes
SCIF0 has been enabled by the firmware, so it worked already. Still, add
the proper nodes to make it work in any case.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121110008.15894-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 597676ee4deb..c0df0e7f32b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -83,6 +83,9 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + avb0_pins: avb0 { mux { groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; @@ -115,8 +118,26 @@ groups = "i2c6"; function = "i2c6"; }; + + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; }; &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; status = "okay"; }; + +&scif_clk { + clock-frequency = <24000000>; +}; |