diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-06-14 21:30:05 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-17 09:46:20 +0200 |
| commit | 1614c8624a48b9c9161b2071e9e727bf5a1817ef (patch) | |
| tree | 19fc1903c9048bfde6aeda25c6675f2026fa3c9e /arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | |
| parent | 40753144256b63b4e3fb9d80874605dda16ad713 (diff) | |
arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector
The schematics label it as SCIF0 debug port.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614193005.2652-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 41aa8591b3b1..81d178e69527 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -60,6 +60,11 @@ function = "scif3"; }; + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; @@ -79,6 +84,14 @@ status = "okay"; }; +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &scif_clk { clock-frequency = <24000000>; }; |