diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-02-06 00:21:36 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-06 10:50:29 +0100 |
| commit | 8b6a006c914aac1702ef85b4ea42ff566b157c85 (patch) | |
| tree | 8f382731544f9dc9fadc3313277fbc0dabf0111e /arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | |
| parent | c2b92d7e90187faaa98f6312984724f27401af03 (diff) | |
arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems
The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi index 9d89d4590358..9cf27ca9f1d2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi @@ -15,11 +15,4 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; |