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authorPierre Gondois <pierre.gondois@arm.com>2022-11-07 16:57:11 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-11-08 14:33:09 +0100
commit4662d6e8c9b0035581ffc31cab80ea5963bd9f24 (patch)
tree38e587183d90b181257a92049ff04e9c02368317 /arch/arm64/boot/dts/renesas/r9a07g054.dtsi
parent40a6dd7b94172d9fce1dec99e8c0345491990970 (diff)
arm64: dts: renesas: rzg2l: Add missing cache-level properties
The DeviceTree Specification v0.3 specifies that the cache node 'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes. Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221107155825.1644604-19-pierre.gondois@arm.com [geert: Update description] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g054.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r9a07g054.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 7c7bbe377699..a36f33376ae3 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -109,6 +109,7 @@
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};