diff options
author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-12 17:13:14 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 13:56:09 +0200 |
commit | 895199bc4e5261b67b688a915c592dd4c3af113c (patch) | |
tree | d82f514a0aee4361122f47b7a8b48d9883f7f4a0 /arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | |
parent | cf40c9689e5109bf5e4c29038c9f450223aaad2b (diff) |
arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
- memory
- External input clock
- CPG
- DMA
- SCIF
It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi new file mode 100644 index 000000000000..3bbb8fcd604c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC SOM common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + chosen { + bootargs = "ignore_loglevel"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; |