diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-01-02 22:18:15 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-01-26 16:03:03 +0100 |
| commit | f4673e52dbab9d890d236ed75264653bcd43bac1 (patch) | |
| tree | 69349a84177d8f2d0636aa3c630400ddd71cb1c7 /arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | |
| parent | 85169df721078bf90fb0fc3bf15e4743fea45b2d (diff) | |
arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
ETH1 respectively.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102221815.273719-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 931efc07d6fb..49ecd33aeeb8 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { @@ -77,6 +78,8 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -104,6 +107,8 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -151,7 +156,8 @@ <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */ }; eth1_pins: eth1 { @@ -169,7 +175,8 @@ <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */ }; sdhi0_emmc_pins: sd0emmc { |