diff options
| author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2023-03-31 16:14:31 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-04-04 10:01:01 +0200 |
| commit | 741f99c7ff7c508cfc0ede760ea089993b2327c3 (patch) | |
| tree | 38c46f049e9c895dfcb19b8b370bd60735ec68ff /arch/arm64/boot/dts/renesas | |
| parent | 166e023478696be40af1dd639af7ac89fea09003 (diff) | |
arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712
Specify the bus-type property for all three connected MAX96712.
The default behavior when parsing a node without this property is to
default to D-PHY. Making this explicit plays it safe and future proofs
things as the default parsing comes from the V4L2 core and not the
driver itself.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230331141431.3820311-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index e06b8eda85e1..dbc8dcab109d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2021 Glider bv */ +#include <dt-bindings/media/video-interfaces.h> + &csi40 { status = "okay"; @@ -105,6 +107,7 @@ port@4 { reg = <4>; max96712_out0: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; clock-lanes = <0>; data-lanes = <1 2 3 4>; remote-endpoint = <&csi40_in>; @@ -125,6 +128,7 @@ port@4 { reg = <4>; max96712_out1: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; @@ -146,6 +150,7 @@ port@4 { reg = <4>; max96712_out2: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; |