diff options
| author | Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-02-01 15:19:18 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-22 11:03:32 +0100 |
| commit | ad761924be2b33555e7d6b99a0b3b0c8384f549b (patch) | |
| tree | 3fbaf964af8dacda96432d792f07c0c745ef481f /arch/arm64/boot/dts/renesas | |
| parent | 5db13ece46d6948d5c26429c2827a78ed3a5afc5 (diff) | |
arm64: dts: renesas: r8a779h0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A76 on R-Car V4M.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/848d176bdbcaf3bc44e5dae555afa9c812a19fd1.1706796979.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 88c5dcbc38d5..b3255bba69e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -42,6 +42,7 @@ power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_1: cpu@100 { @@ -51,6 +52,7 @@ power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_2: cpu@200 { @@ -60,6 +62,7 @@ power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_3: cpu@300 { @@ -69,6 +72,20 @@ power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; }; L3_CA76: cache-controller { |