diff options
| author | Chris Morgan <macromorgan@hotmail.com> | 2023-03-27 10:35:47 -0500 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-03-30 13:27:33 +0200 |
| commit | 87891399d9883ed823ba58c2be3ac20cc499ad7d (patch) | |
| tree | aedcd94e4f7fa050aad77d82f0dbc5a03007c631 /arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts | |
| parent | b37115b6534c4027df75854a44b485596d368171 (diff) | |
arm64: dts: rockchip: Add clk_rtc_32k to Anbernic xx3 Devices
For the Anbernic devices to display properly, we need to specify the
clock frequency of the PLL_VPLL. Adding the parent clock in the
rk356x.dtsi requires us to update our clock definitions to accomplish
this.
Fixes: 64b69474edf3 ("arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20230327153547.821822-1-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts index b4b2df821cba..c763c7f3b1b3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts @@ -105,8 +105,10 @@ }; &cru { - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; - assigned-clock-rates = <1200000000>, <200000000>, <500000000>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <500000000>; }; &dsi_dphy0 { |