diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2021-01-21 11:26:57 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-02-01 10:36:34 +0100 |
| commit | cbf8bed0e353516653d90b30ff20ac3318596d83 (patch) | |
| tree | 346eb409de694e9ddeda25bcb3dab43eb878ff1a /arch/arm64/boot/dts/xilinx | |
| parent | 41b452a5702b4a35b4ddb12a83ca21875e366d50 (diff) | |
arm64: dts: zynqmp: Wire zynqmp qspi controller
Add missing ZynqMP qspi IP. It works in single mode only.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 14 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 7af57619436d..6a577e1383c1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -164,6 +164,10 @@ clocks = <&zynqmp_clk PCIE_REF>; }; +&qspi { + clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; +}; + &sata { clocks = <&zynqmp_clk SATA_REF>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 19b349f00ce7..533c19b80283 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -595,6 +595,20 @@ }; }; + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + status = "disabled"; + clock-names = "ref_clk", "pclk"; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x0 0x1000>, + <0x0 0xc0000000 0x0 0x8000000>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&zynqmp_firmware PD_QSPI>; + }; + psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; |