diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-06-28 10:59:19 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:30:07 +0100 |
| commit | ed93a666bb32cb35a0f4c42bf9f63a047a90d475 (patch) | |
| tree | ae3a4bac7a56700c2d980a9102242eeaebe80ccb /arch/arm64/boot/dts | |
| parent | b7450f161f8ab91abeafaadafe05517a6ffbb26c (diff) | |
arm64: tegra: Add SOR0_OUT clock on Tegra210
This clock was not previously used because it is a fixed clock. However,
adding it here allows operating systems to deal with SOR0 the same way
as SOR1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d21cf2758d27..a20cd368a772 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -254,10 +254,11 @@ reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_SOR0>, + <&tegra_car TEGRA210_CLK_SOR0_OUT>, <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, <&tegra_car TEGRA210_CLK_PLL_DP>, <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; pinctrl-0 = <&state_dpaux_aux>; |