diff options
| author | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2016-11-03 21:07:20 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-11-21 10:18:47 +0100 |
| commit | d92ce1a57480e17aff1fb8693cc919bb46a6e0fd (patch) | |
| tree | fba1107d17062481c7117bbb61cdf7c500ea66d0 /arch/arm64/boot | |
| parent | d9b1c753878310c90e8be178f6a8e119fd0aa25d (diff) | |
arm64: dts: m3ulcb: enable SCIF clk and pins
This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index 1ae0708bb495..96cda59c2698 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -37,10 +37,18 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; }; &scif2 { @@ -49,3 +57,8 @@ status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; |