diff options
| author | Will Deacon <will.deacon@arm.com> | 2018-06-14 11:21:34 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-06 16:47:04 +0000 |
| commit | bd4fb6d270bc423a9a4098108784f7f9254c4e6d (patch) | |
| tree | b795cee624fd00a3274c5d6efd89df71288cf1ff /arch/arm64/include/asm/barrier.h | |
| parent | 0b587c84e42151fc5a636c7cebf7b03b281dc672 (diff) | |
arm64: Add support for SB barrier and patch in over DSB; ISB sequences
We currently use a DSB; ISB sequence to inhibit speculation in set_fs().
Whilst this works for current CPUs, future CPUs may implement a new SB
barrier instruction which acts as an architected speculation barrier.
On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB
sequence and advertise the presence of the new instruction to userspace.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/barrier.h')
| -rw-r--r-- | arch/arm64/include/asm/barrier.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 822a9192c551..f66bb04fdf2d 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -34,6 +34,10 @@ #define psb_csync() asm volatile("hint #17" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") +#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \ + SB_BARRIER_INSN"nop\n", \ + ARM64_HAS_SB)) + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st) |