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authorMarc Zyngier <maz@kernel.org>2023-12-18 17:07:34 +0000
committerMarc Zyngier <maz@kernel.org>2023-12-18 17:07:34 +0000
commit189f2c8e0c420b194af0ee22b8f247948cb577be (patch)
tree4766a8eb3c66fbfdc5deb53ad153e03e6d4c71ca /arch/arm64/include/asm/kvm_arm.h
parent2cc14f52aeb78ce3f29677c2de1f06c0e91471ab (diff)
parent11e5ea5242e38d44fcede879473566bb6d68f954 (diff)
Merge branch kvm-arm64/lpa2 into kvmarm-master/next
* kvm-arm64/lpa2: : . : Support FEAT_LPA2 at EL2 S1 and S2, courtesy of Ryan Roberts : : From the cover letter: : : "This adds support for FEAT_LPA2 to KVM for both hypervisor stage 1 (for the : nvhe/protected modes) and the vm stage 2 translation tables (for all modes). : FEAT_LPA2 enables 52 bit PAs and VAs for 4KB and 16KB granules (note this is : already supported for 64KB granules via the FEAT_LPA and FEAT_LVA extensions)." : . KVM: arm64: Use helpers to classify exception types reported via ESR KVM: selftests: arm64: Support P52V48 4K and 16K guest_modes KVM: selftests: arm64: Determine max ipa size per-page size KVM: arm64: Allow guests with >48-bit IPA size on FEAT_LPA2 systems KVM: arm64: Support up to 5 levels of translation in kvm_pgtable KVM: arm64: Convert translation level parameter to s8 KVM: arm64: Use LPA2 page-tables for stage2 and hyp stage1 KVM: arm64: Add new (V)TCR_EL2 field definitions for FEAT_LPA2 arm64: Add ARM64_HAS_LPA2 CPU capability arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] arm64/mm: Update tlb invalidation routines for FEAT_LPA2 arm64/mm: Add lpa2_is_enabled() kvm_lpa2_is_enabled() stubs arm64/mm: Modify range-based tlbi to decrement scale Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/kvm_arm.h')
-rw-r--r--arch/arm64/include/asm/kvm_arm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index b85f46a73e21..312cbc300831 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -108,6 +108,7 @@
#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)
/* TCR_EL2 Registers bits */
+#define TCR_EL2_DS (1UL << 32)
#define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
#define TCR_EL2_TBI (1 << 20)
#define TCR_EL2_PS_SHIFT 16
@@ -122,6 +123,7 @@
TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
/* VTCR_EL2 Registers bits */
+#define VTCR_EL2_DS TCR_EL2_DS
#define VTCR_EL2_RES1 (1U << 31)
#define VTCR_EL2_HD (1 << 22)
#define VTCR_EL2_HA (1 << 21)