diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-06-28 18:07:32 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2016-07-01 11:46:00 +0100 |
| commit | 7dd01aef055792260287c6708daf75aac3918f66 (patch) | |
| tree | f064a41ff4949170f335e4fd495cdafb9d810903 /arch/arm64/include/asm/processor.h | |
| parent | 390bf1773c7eba3b45df62ae82b3d2be911185b7 (diff) | |
arm64: trap userspace "dc cvau" cache operation on errata-affected core
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac". Since we allow userspace to also emit those instructions,
we should make sure that "dc cvau" gets promoted there too.
So lets grasp the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault back into userspace.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/processor.h')
| -rw-r--r-- | arch/arm64/include/asm/processor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index cef1cf398356..ace0a96e7d6e 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -192,5 +192,6 @@ static inline void spin_lock_prefetch(const void *ptr) void cpu_enable_pan(void *__unused); void cpu_enable_uao(void *__unused); +void cpu_enable_cache_maint_trap(void *__unused); #endif /* __ASM_PROCESSOR_H */ |