diff options
| author | Will Deacon <will.deacon@arm.com> | 2017-03-10 20:32:22 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-03-20 16:16:57 +0000 |
| commit | 155433cb365ee4666bdf7c3c7bc2978b17be36a4 (patch) | |
| tree | 43668ce6b2cfffb1327fe5c1054ddc228a108f1a /arch/arm64/include | |
| parent | a8d4636f96ad075dc6d6af182b3de0b5498dc301 (diff) | |
arm64: cache: Remove support for ASID-tagged VIVT I-caches
As a recent change to ARMv8, ASID-tagged VIVT I-caches are removed
retrospectively from the architecture. Consequently, we don't need to
support them in Linux either.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/cachetype.h | 8 | ||||
| -rw-r--r-- | arch/arm64/include/asm/kvm_mmu.h | 2 |
2 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index 212a0f3d4ecb..fbab37c669a0 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -23,8 +23,6 @@ #define CTR_CWG_SHIFT 24 #define CTR_CWG_MASK 15 -#define ICACHE_POLICY_RESERVED 0 -#define ICACHE_POLICY_AIVIVT 1 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 @@ -35,7 +33,6 @@ #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) #define ICACHEF_ALIASING 0 -#define ICACHEF_AIVIVT 1 extern unsigned long __icache_flags; @@ -48,11 +45,6 @@ static inline int icache_is_aliasing(void) return test_bit(ICACHEF_ALIASING, &__icache_flags); } -static inline int icache_is_aivivt(void) -{ - return test_bit(ICACHEF_AIVIVT, &__icache_flags); -} - static inline u32 cache_type_cwg(void) { return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index ed1246014901..4be5773d4606 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -245,7 +245,7 @@ static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, if (!icache_is_aliasing()) { /* PIPT */ flush_icache_range((unsigned long)va, (unsigned long)va + size); - } else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */ + } else { /* any kind of VIPT cache */ __flush_icache_all(); } |