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authorCatalin Marinas <catalin.marinas@arm.com>2016-07-01 15:48:55 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2016-11-21 17:33:47 +0000
commitf33bcf03e6079668da6bf4eec4a7dcf9289131d0 (patch)
tree7ac9ba9224f5d1f56233347bfe23e58b58f1645b /arch/arm64/mm
parentbd38967d406fb4f9fca67d612db71b5d74cfb0f5 (diff)
arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro
This patch takes the errata workaround code out of cpu_do_switch_mm into a dedicated post_ttbr0_update_workaround macro which will be reused in a subsequent patch. Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Kees Cook <keescook@chromium.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
-rw-r--r--arch/arm64/mm/proc.S6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 6a853a867d9e..32682be978e0 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -142,11 +142,7 @@ ENTRY(cpu_do_switch_mm)
bfi x0, x1, #48, #16 // set the ASID
msr ttbr0_el1, x0 // set TTBR0
isb
-alternative_if ARM64_WORKAROUND_CAVIUM_27456
- ic iallu
- dsb nsh
- isb
-alternative_else_nop_endif
+ post_ttbr0_update_workaround
ret
ENDPROC(cpu_do_switch_mm)