diff options
| author | Jerin Jacob <jerinj@marvell.com> | 2019-09-02 11:44:48 +0530 |
|---|---|---|
| committer | Daniel Borkmann <daniel@iogearbox.net> | 2019-09-03 15:44:40 +0200 |
| commit | 504792e07a44844f24e9d79913e4a2f8373cd332 (patch) | |
| tree | 2a1df20689ac52cb0fd6b063f1bf8127dcddd503 /arch/arm64/net/bpf_jit.h | |
| parent | 53092f7e074936df43aa4dbf4b6c3df812f3dab9 (diff) | |
arm64: bpf: optimize modulo operation
Optimize modulo operation instruction generation by
using single MSUB instruction vs MUL followed by SUB
instruction scheme.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Diffstat (limited to 'arch/arm64/net/bpf_jit.h')
| -rw-r--r-- | arch/arm64/net/bpf_jit.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h index cb7ab50b7657..eb73f9f72c46 100644 --- a/arch/arm64/net/bpf_jit.h +++ b/arch/arm64/net/bpf_jit.h @@ -171,6 +171,9 @@ /* Rd = Ra + Rn * Rm */ #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \ A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD) +/* Rd = Ra - Rn * Rm */ +#define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \ + A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB) /* Rd = Rn * Rm */ #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm) |