diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-06-21 20:23:06 +0900 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2019-07-30 09:05:14 -0500 |
| commit | c1459a9d7e920b045aa3eb458ee099dc76f50502 (patch) | |
| tree | e5b6d41a9bf481d57d08c89ac85019a4376e94a1 /arch/arm | |
| parent | e10c18484b66afa830f9a36348e12143f0ec2267 (diff) | |
ARM: dts: socfpga: update to new Denali NAND binding
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
and NAND chips"), the Denali NAND controller driver migrated to the
new controller/chip representation.
Update DT for it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 20 |
3 files changed, 15 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index ec1966480f2f..90d6d0d4417d 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -747,7 +747,7 @@ nand0: nand@ff900000 { #address-cells = <0x1>; - #size-cells = <0x1>; + #size-cells = <0x0>; compatible = "altr,socfpga-denali-nand"; reg = <0xff900000 0x100000>, <0xffb80000 0x10000>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 26c157b91189..2a86e72d9791 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -662,7 +662,7 @@ nand: nand@ffb90000 { #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; compatible = "altr,socfpga-denali-nand"; reg = <0xffb90000 0x72000>, <0xffb80000 0x10000>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index e36e0a0f8aa6..9bd9e04c7361 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -9,12 +9,18 @@ &nand { status = "okay"; - partition@nand-boot { - label = "Boot and fpga data"; - reg = <0x0 0x1C00000>; - }; - partition@nand-rootfs { - label = "Root Filesystem - JFFS2"; - reg = <0x1C00000 0x6400000>; + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x1C00000>; + }; + partition@1c00000 { + label = "Root Filesystem - JFFS2"; + reg = <0x1C00000 0x6400000>; + }; }; }; |