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authorAndreas Färber <afaerber@suse.de>2017-06-05 21:20:17 +0200
committerAndreas Färber <afaerber@suse.de>2017-11-04 18:12:23 +0800
commit4dc8bf927c3d50885dab14c1e3dd21b797cf3c24 (patch)
treeaf44c18ba514d1141746a03d8a014e00996cfa02 /arch/arm
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff)
ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
CPU2 has its own power domain PD_CPU2, and CPU3 has PD_CPU3. Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/owl-s500.dtsi3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 51a48741d4c0..43c9980a4260 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/owl-s500-powergate.h>
/ {
compatible = "actions,s500";
@@ -43,6 +44,7 @@
compatible = "arm,cortex-a9";
reg = <0x2>;
enable-method = "actions,s500-smp";
+ power-domains = <&sps S500_PD_CPU2>;
};
cpu3: cpu@3 {
@@ -50,6 +52,7 @@
compatible = "arm,cortex-a9";
reg = <0x3>;
enable-method = "actions,s500-smp";
+ power-domains = <&sps S500_PD_CPU3>;
};
};