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authorAfzal Mohammed <afzal.mohd.ma@gmail.com>2017-02-01 13:47:34 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2017-02-28 11:06:15 +0000
commitad475117d2015781789364d599b85c67254680a1 (patch)
tree52e0a270251c3d2283e1ca44957da424ce1e62e9 /arch/arm
parent58c16709f9cad7e6daabeaa5c94ac4dcb260aedd (diff)
ARM: 8649/2: nommu: remove Hivecs configuration is asm
Now that exception based address is handled dynamically for processors with CP15, remove Hivecs configuration in assembly. Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/kernel/head-nommu.S5
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6b4eb27b8758..2e21e08de747 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -152,11 +152,6 @@ __after_proc_init:
#ifdef CONFIG_CPU_ICACHE_DISABLE
bic r0, r0, #CR_I
#endif
-#ifdef CONFIG_CPU_HIGH_VECTOR
- orr r0, r0, #CR_V
-#else
- bic r0, r0, #CR_V
-#endif
mcr p15, 0, r0, c1, c0, 0 @ write control reg
#elif defined (CONFIG_CPU_V7M)
/* For V7M systems we want to modify the CCR similarly to the SCTLR */