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authorGregory CLEMENT <gregory.clement@free-electrons.com>2014-04-14 17:10:06 +0200
committerJason Cooper <jason@lakedaemon.net>2014-05-08 16:18:51 +0000
commitb41375f71aceadb7d74a18aafba4da5024fc104b (patch)
treeef79aa21f36ad88f8c44ba31b19bbc07df2d3bd3 /arch/arm
parentccd6a13180193700067bfdac5f7d7b436d757382 (diff)
ARM: mvebu: ll_set_cpu_coherent always uses the current CPU
ll_set_cpu_coherent is always used on the current CPU, so instead of passing the CPU id as argument, ll_set_cpu_coherent() can find it by itself. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-mvebu/coherency.c12
-rw-r--r--arch/arm/mach-mvebu/coherency.h2
-rw-r--r--arch/arm/mach-mvebu/coherency_ll.S10
-rw-r--r--arch/arm/mach-mvebu/headsmp.S4
-rw-r--r--arch/arm/mach-mvebu/platsmp.c2
5 files changed, 12 insertions, 18 deletions
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 615dc0b6093e..2df90c998820 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -61,17 +61,17 @@ static struct of_device_id of_coherency_table[] = {
};
/* Function defined in coherency_ll.S */
-int ll_set_cpu_coherent(unsigned int hw_cpu_id);
+int ll_set_cpu_coherent(void);
-int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
+int set_cpu_coherent(int smp_group_id)
{
if (!coherency_base) {
- pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
+ pr_warn("Can't make current CPU cache coherent.\n");
pr_warn("Coherency fabric is not initialized\n");
return 1;
}
- return ll_set_cpu_coherent(hw_cpu_id);
+ return ll_set_cpu_coherent();
}
/*
@@ -302,7 +302,7 @@ static void __init armada_370_coherency_init(struct device_node *np)
sync_cache_w(&coherency_phys_base);
coherency_base = of_iomap(np, 0);
coherency_cpu_base = of_iomap(np, 1);
- set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+ set_cpu_coherent(0);
}
static void __init armada_375_380_coherency_init(struct device_node *np)
@@ -330,8 +330,6 @@ static int coherency_type(void)
/* Armada 380 coherency works only on SMP */
else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
return type;
-
- of_node_put(np);
}
return COHERENCY_FABRIC_TYPE_NONE;
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 02f7ec34ced2..ab594a75fef3 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -16,7 +16,7 @@
extern unsigned long coherency_phys_base;
-int set_cpu_coherent(unsigned int cpu_id, int smp_group_id);
+int set_cpu_coherent(int smp_group_id);
int coherency_init(void);
int coherency_available(void);
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 1f2bcd4b5424..98a0b73f909b 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -24,9 +24,7 @@
#include <asm/cp15.h>
.text
-/*
- * r0: HW CPU id
- */
+
ENTRY(ll_set_cpu_coherent)
mrc p15, 0, r1, c1, c0, 0
tst r1, #CR_M @ Check MMU bit enabled
@@ -43,8 +41,10 @@ ENTRY(ll_set_cpu_coherent)
ldr r0, [r0]
2:
/* Create bit by cpu index */
- mov r3, #(1 << 24)
- lsl r1, r3, r1
+ mrc 15, 0, r1, cr0, cr0, 5
+ and r1, r1, #15
+ mov r2, #(1 << 24)
+ lsl r1, r2, r1
ARM_BE8(rev r1, r1)
/* Add CPU to SMP group - Atomic */
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index f30bc8d78871..cf7abe6554f7 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -31,10 +31,6 @@
ENTRY(armada_xp_secondary_startup)
ARM_BE8(setend be ) @ go BE8 if entered LE
- /* Read CPU id */
- mrc p15, 0, r1, c0, c0, 5
- and r1, r1, #0xF
-
/* Add CPU to coherency fabric */
bl ll_set_cpu_coherent
b secondary_startup
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 32bf78e80c48..75436c0023a8 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -103,7 +103,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
set_secondary_cpus_clock();
flush_cache_all();
- set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+ set_cpu_coherent(0);
/*
* In order to boot the secondary CPUs we need to ensure