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authorLinus Torvalds <torvalds@linux-foundation.org>2022-04-01 13:21:19 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2022-04-01 13:21:19 -0700
commitba2d6201a9bfb1c5d5bfbc58a2db73d051b8337a (patch)
treee7334df56a6c8ff0f337b5e6c7449ee96791edc5 /arch/arm
parentb012b3235cb9d05e4ccaff8327bfbed6faf014aa (diff)
parenteeeb4f1075d71d67083c75f69247206e9b3d9f4a (diff)
Merge tag 'soc-fixes-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd BergmannL "The introduction of vmap-stack on 32-bit arm caused a regression on a few omap3/omap4 machines that pass a stack variable into a firmware interface. The early pre-ACPI AMD Seattle machines have been broken for a while, Ard Biesheuvel has a series to bring them back for now. A few machines with multiple DMA channels used on a device have the channels in the wrong order according to the binding, which causes a harmless warning. Reversing the order is easier than fixing the tools to suppress the warning" * tag 'soc-fixes-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: ls1046a: Update i2c node dma properties arm64: dts: ls1043a: Update i2c dma properties ARM: dts: spear1340: Update serial node properties ARM: dts: spear13xx: Update SPI dma properties ARM: OMAP2+: Fix regression for smc calls for vmap stack dt: amd-seattle: add a description of the CPUs and caches dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0 dt: amd-seattle: add description of the SATA/CCP SMMUs dt: amd-seattle: add a description of the PCIe SMMU dt: amd-seattle: fix PCIe legacy interrupt routing dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding dt: amd-seattle: remove Overdrive revision A0 support dt: amd-seattle: remove Husky platform
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi6
-rw-r--r--arch/arm/boot/dts/spear13xx.dtsi6
-rw-r--r--arch/arm/mach-omap2/omap-secure.c13
3 files changed, 16 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 827e887afbda..13e1bdb3ddbf 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -134,9 +134,9 @@
reg = <0xb4100000 0x1000>;
interrupts = <0 105 0x4>;
status = "disabled";
- dmas = <&dwdma0 12 0 1>,
- <&dwdma0 13 1 0>;
- dma-names = "tx", "rx";
+ dmas = <&dwdma0 13 0 1>,
+ <&dwdma0 12 1 0>;
+ dma-names = "rx", "tx";
};
thermal@e07008c4 {
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index c87b881b2c8b..913553367687 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -284,9 +284,9 @@
#size-cells = <0>;
interrupts = <0 31 0x4>;
status = "disabled";
- dmas = <&dwdma0 4 0 0>,
- <&dwdma0 5 0 0>;
- dma-names = "tx", "rx";
+ dmas = <&dwdma0 5 0 0>,
+ <&dwdma0 4 0 0>;
+ dma-names = "rx", "tx";
};
rtc@e0580000 {
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index 0659ab4cb0af..11677fc2968f 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -59,8 +59,13 @@ static void __init omap_optee_init_check(void)
u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
u32 arg3, u32 arg4)
{
+ static u32 buf[NR_CPUS][5];
+ u32 *param;
+ int cpu;
u32 ret;
- u32 param[5];
+
+ cpu = get_cpu();
+ param = buf[cpu];
param[0] = nargs;
param[1] = arg1;
@@ -76,6 +81,8 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
outer_clean_range(__pa(param), __pa(param + 5));
ret = omap_smc2(idx, flag, __pa(param));
+ put_cpu();
+
return ret;
}
@@ -119,8 +126,8 @@ phys_addr_t omap_secure_ram_mempool_base(void)
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
u32 omap3_save_secure_ram(void __iomem *addr, int size)
{
+ static u32 param[5];
u32 ret;
- u32 param[5];
if (size != OMAP3_SAVE_SECURE_RAM_SZ)
return OMAP3_SAVE_SECURE_RAM_SZ;
@@ -153,8 +160,8 @@ u32 omap3_save_secure_ram(void __iomem *addr, int size)
u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4)
{
+ static u32 param[5];
u32 ret;
- u32 param[5];
param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
param[1] = arg1;