arch: remove blackfin port

The Analog Devices Blackfin port was added in 2007 and was rather
active for a while, but all work on it has come to a standstill
over time, as Analog have changed their product line-up.

Aaron Wu confirmed that the architecture port is no longer relevant,
and multiple people suggested removing blackfin independently because
of some of its oddities like a non-working SMP port, and the amount of
duplication between the chip variants, which cause extra work when
doing cross-architecture changes.

Link: https://docs.blackfin.uclinux.org/
Acked-by: Aaron Wu <Aaron.Wu@analog.com>
Acked-by: Bryan Wu <cooloney@gmail.com>
Cc: Steven Miao <realmz6@gmail.com>
Cc: Mike Frysinger <vapier@chromium.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

3 files changed, 0 insertions, 450 deletions

diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
deleted file mode 100644
index 81baa27bc389..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
-		    -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
-		    -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
-		    -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
deleted file mode 100644
index b49a53b583d5..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-
-int first_switched_icplb PDT_ATTR;
-int first_switched_dcplb PDT_ATTR;
-
-struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
-struct cplb_boundary icplb_bounds[9] PDT_ATTR;
-
-int icplb_nr_bounds PDT_ATTR;
-int dcplb_nr_bounds PDT_ATTR;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
-	int i_d, i_i;
-	unsigned long addr;
-	unsigned long cplb_pageflags, cplb_pagesize;
-
-	struct cplb_entry *d_tbl = dcplb_tbl[cpu];
-	struct cplb_entry *i_tbl = icplb_tbl[cpu];
-
-	printk(KERN_INFO "NOMPU: setting up cplb tables\n");
-
-	i_d = i_i = 0;
-
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
-	/* Set up the zero page.  */
-	d_tbl[i_d].addr = 0;
-	d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-	i_tbl[i_i].addr = 0;
-	i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-#endif
-
-	/* Cover kernel memory with 4M pages.  */
-	addr = 0;
-
-#ifdef PAGE_SIZE_16MB
-	cplb_pageflags = PAGE_SIZE_16MB;
-	cplb_pagesize = SIZE_16M;
-#else
-	cplb_pageflags = PAGE_SIZE_4MB;
-	cplb_pagesize = SIZE_4M;
-#endif
-
-
-	for (; addr < memory_start; addr += cplb_pagesize) {
-		d_tbl[i_d].addr = addr;
-		d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
-		i_tbl[i_i].addr = addr;
-		i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
-	}
-
-#ifdef CONFIG_ROMKERNEL
-	/* Cover kernel XIP flash area */
-#ifdef CONFIG_BF60x
-	addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
-	d_tbl[i_d].addr = addr;
-	d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
-	i_tbl[i_i].addr = addr;
-	i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
-#else
-	addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
-	d_tbl[i_d].addr = addr;
-	d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
-	i_tbl[i_i].addr = addr;
-	i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
-#endif
-#endif
-
-	/* Cover L1 memory.  One 4M area for code and data each is enough.  */
-	if (cpu == 0) {
-		if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
-			d_tbl[i_d].addr = L1_DATA_A_START;
-			d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
-		}
-		i_tbl[i_i].addr = L1_CODE_START;
-		i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-	}
-#ifdef CONFIG_SMP
-	else {
-		if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
-			d_tbl[i_d].addr = COREB_L1_DATA_A_START;
-			d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
-		}
-		i_tbl[i_i].addr = COREB_L1_CODE_START;
-		i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-	}
-#endif
-	first_switched_dcplb = i_d;
-	first_switched_icplb = i_i;
-
-	BUG_ON(first_switched_dcplb > MAX_CPLBS);
-	BUG_ON(first_switched_icplb > MAX_CPLBS);
-
-	while (i_d < MAX_CPLBS)
-		d_tbl[i_d++].data = 0;
-	while (i_i < MAX_CPLBS)
-		i_tbl[i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
-	unsigned long uncached_end;
-	int i_d, i_i;
-
-	i_d = 0;
-	/* Normal RAM, including MTD FS.  */
-#ifdef CONFIG_MTD_UCLINUX
-	uncached_end = memory_mtd_start + mtd_size;
-#else
-	uncached_end = memory_end;
-#endif
-	/*
-	 * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
-	 * so that we don't have to use 4kB pages and cause CPLB thrashing
-	 */
-	if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
-	    ((_ramend - uncached_end) >= 1 * 1024 * 1024))
-		dcplb_bounds[i_d].eaddr = uncached_end;
-	else
-		dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
-	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
-	/* DMA uncached region.  */
-	if (DMA_UNCACHED_REGION) {
-		dcplb_bounds[i_d].eaddr = _ramend;
-		dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
-	}
-	if (_ramend != physical_mem_end) {
-		/* Reserved memory.  */
-		dcplb_bounds[i_d].eaddr = physical_mem_end;
-		dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
-					    SDRAM_DGENERIC : SDRAM_DNON_CHBL);
-	}
-	/* Addressing hole up to the async bank.  */
-	dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
-	dcplb_bounds[i_d++].data = 0;
-	/* ASYNC banks.  */
-	dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
-	dcplb_bounds[i_d++].data = SDRAM_EBIU;
-	/* Addressing hole up to BootROM.  */
-	dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
-	dcplb_bounds[i_d++].data = 0;
-	/* BootROM -- largest one should be less than 1 meg.  */
-	dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
-	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
-	if (L2_LENGTH) {
-		/* Addressing hole up to L2 SRAM.  */
-		dcplb_bounds[i_d].eaddr = L2_START;
-		dcplb_bounds[i_d++].data = 0;
-		/* L2 SRAM.  */
-		dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
-		dcplb_bounds[i_d++].data = L2_DMEMORY;
-	}
-	dcplb_nr_bounds = i_d;
-	BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
-
-	i_i = 0;
-	/* Normal RAM, including MTD FS.  */
-	icplb_bounds[i_i].eaddr = uncached_end;
-	icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-	if (_ramend != physical_mem_end) {
-		/* DMA uncached region.  */
-		if (DMA_UNCACHED_REGION) {
-			/* Normally this hole is caught by the async below.  */
-			icplb_bounds[i_i].eaddr = _ramend;
-			icplb_bounds[i_i++].data = 0;
-		}
-		/* Reserved memory.  */
-		icplb_bounds[i_i].eaddr = physical_mem_end;
-		icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
-					    SDRAM_IGENERIC : SDRAM_INON_CHBL);
-	}
-	/* Addressing hole up to the async bank.  */
-	icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
-	icplb_bounds[i_i++].data = 0;
-	/* ASYNC banks.  */
-	icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
-	icplb_bounds[i_i++].data = SDRAM_EBIU;
-	/* Addressing hole up to BootROM.  */
-	icplb_bounds[i_i].eaddr = BOOT_ROM_START;
-	icplb_bounds[i_i++].data = 0;
-	/* BootROM -- largest one should be less than 1 meg.  */
-	icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
-	icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-
-	if (L2_LENGTH) {
-		/* Addressing hole up to L2 SRAM.  */
-		icplb_bounds[i_i].eaddr = L2_START;
-		icplb_bounds[i_i++].data = 0;
-		/* L2 SRAM.  */
-		icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
-		icplb_bounds[i_i++].data = L2_IMEMORY;
-	}
-	icplb_nr_bounds = i_i;
-	BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
deleted file mode 100644
index 79cc0f6dcdd5..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Based on:     arch/blackfin/kernel/cplb-mpu/cplbmgr.c
- * Author:       Michael McTernan <mmcternan@airvana.com>
- *
- * Description:  CPLB miss handler.
- *
- * Modified:
- *               Copyright 2008 Airvana Inc.
- *               Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/cplb.h>
-#include <asm/mmu_context.h>
-#include <asm/traps.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options.  We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
-int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
-				    unsigned long addr)
-{
-	_disable_dcplb();
-	bfin_write32(DCPLB_DATA0 + idx * 4, data);
-	bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
-	_enable_dcplb();
-
-#ifdef CONFIG_CPLB_INFO
-	dcplb_tbl[cpu][idx].addr = addr;
-	dcplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-static inline void write_icplb_data(int cpu, int idx, unsigned long data,
-				    unsigned long addr)
-{
-	_disable_icplb();
-	bfin_write32(ICPLB_DATA0 + idx * 4, data);
-	bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
-	_enable_icplb();
-
-#ifdef CONFIG_CPLB_INFO
-	icplb_tbl[cpu][idx].addr = addr;
-	icplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-/* Counters to implement round-robin replacement.  */
-static int icplb_rr_index[NR_CPUS] PDT_ATTR;
-static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-static int evict_one_icplb(int cpu)
-{
-	int i = first_switched_icplb + icplb_rr_index[cpu];
-	if (i >= MAX_CPLBS) {
-		i -= MAX_CPLBS - first_switched_icplb;
-		icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
-	}
-	icplb_rr_index[cpu]++;
-	return i;
-}
-
-static int evict_one_dcplb(int cpu)
-{
-	int i = first_switched_dcplb + dcplb_rr_index[cpu];
-	if (i >= MAX_CPLBS) {
-		i -= MAX_CPLBS - first_switched_dcplb;
-		dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
-	}
-	dcplb_rr_index[cpu]++;
-	return i;
-}
-
-MGR_ATTR static int icplb_miss(int cpu)
-{
-	unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
-	int status = bfin_read_ICPLB_STATUS();
-	int idx;
-	unsigned long i_data, base, addr1, eaddr;
-
-	nr_icplb_miss[cpu]++;
-	if (unlikely(status & FAULT_USERSUPV))
-		nr_icplb_supv_miss[cpu]++;
-
-	base = 0;
-	idx = 0;
-	do {
-		eaddr = icplb_bounds[idx].eaddr;
-		if (addr < eaddr)
-			break;
-		base = eaddr;
-	} while (++idx < icplb_nr_bounds);
-
-	if (unlikely(idx == icplb_nr_bounds))
-		return CPLB_NO_ADDR_MATCH;
-
-	i_data = icplb_bounds[idx].data;
-	if (unlikely(i_data == 0))
-		return CPLB_NO_ADDR_MATCH;
-
-	addr1 = addr & ~(SIZE_4M - 1);
-	addr &= ~(SIZE_1M - 1);
-	i_data |= PAGE_SIZE_1MB;
-	if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
-		/*
-		 * This works because
-		 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
-		 */
-		i_data |= PAGE_SIZE_4MB;
-		addr = addr1;
-	}
-
-	/* Pick entry to evict */
-	idx = evict_one_icplb(cpu);
-
-	write_icplb_data(cpu, idx, i_data, addr);
-
-	return CPLB_RELOADED;
-}
-
-MGR_ATTR static int dcplb_miss(int cpu)
-{
-	unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
-	int status = bfin_read_DCPLB_STATUS();
-	int idx;
-	unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
-
-	nr_dcplb_miss[cpu]++;
-	if (unlikely(status & FAULT_USERSUPV))
-		nr_dcplb_supv_miss[cpu]++;
-
-	base = 0;
-	idx = 0;
-	do {
-		eaddr = dcplb_bounds[idx].eaddr;
-		if (addr < eaddr)
-			break;
-		base = eaddr;
-	} while (++idx < dcplb_nr_bounds);
-
-	if (unlikely(idx == dcplb_nr_bounds))
-		return CPLB_NO_ADDR_MATCH;
-
-	d_data = dcplb_bounds[idx].data;
-	if (unlikely(d_data == 0))
-		return CPLB_NO_ADDR_MATCH;
-
-	addr &= ~(SIZE_1M - 1);
-	d_data |= PAGE_SIZE_1MB;
-
-	/* BF60x support large than 4M CPLB page size */
-#ifdef PAGE_SIZE_16MB
-	cplb_pageflags = PAGE_SIZE_16MB;
-	cplb_pagesize = SIZE_16M;
-#else
-	cplb_pageflags = PAGE_SIZE_4MB;
-	cplb_pagesize = SIZE_4M;
-#endif
-
-find_pagesize:
-	addr1 = addr & ~(cplb_pagesize - 1);
-	if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
-		/*
-		 * This works because
-		 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
-		 */
-		d_data |= cplb_pageflags;
-		addr = addr1;
-		goto found_pagesize;
-	} else {
-		if (cplb_pagesize > SIZE_4M) {
-			cplb_pageflags = PAGE_SIZE_4MB;
-			cplb_pagesize = SIZE_4M;
-			goto find_pagesize;
-		}
-	}
-
-found_pagesize:
-#ifdef CONFIG_BF60x
-	if ((addr >= ASYNC_BANK0_BASE)
-		&& (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
-		d_data |= PAGE_SIZE_64MB;
-#endif
-
-	/* Pick entry to evict */
-	idx = evict_one_dcplb(cpu);
-
-	write_dcplb_data(cpu, idx, d_data, addr);
-
-	return CPLB_RELOADED;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
-	int cause = seqstat & 0x3f;
-	unsigned int cpu = raw_smp_processor_id();
-	switch (cause) {
-	case VEC_CPLB_I_M:
-		return icplb_miss(cpu);
-	case VEC_CPLB_M:
-		return dcplb_miss(cpu);
-	default:
-		return CPLB_UNKNOWN_ERR;
-	}
-}