diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2018-03-07 22:23:24 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-16 10:55:47 +0100 |
| commit | 4ba66a9760722ccbb691b8f7116cad2f791cca7b (patch) | |
| tree | e29f9624ad0b13aa11860e39440bbc5e24d18a30 /arch/blackfin/mach-bf533 | |
| parent | b8c9c8f0190f4004d3d4364edb2dea5978dfc824 (diff) | |
arch: remove blackfin port
The Analog Devices Blackfin port was added in 2007 and was rather
active for a while, but all work on it has come to a standstill
over time, as Analog have changed their product line-up.
Aaron Wu confirmed that the architecture port is no longer relevant,
and multiple people suggested removing blackfin independently because
of some of its oddities like a non-working SMP port, and the amount of
duplication between the chip variants, which cause extra work when
doing cross-architecture changes.
Link: https://docs.blackfin.uclinux.org/
Acked-by: Aaron Wu <Aaron.Wu@analog.com>
Acked-by: Bryan Wu <cooloney@gmail.com>
Cc: Steven Miao <realmz6@gmail.com>
Cc: Mike Frysinger <vapier@chromium.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/blackfin/mach-bf533')
24 files changed, 0 insertions, 6055 deletions
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig deleted file mode 100644 index 4e1a05be7137..000000000000 --- a/arch/blackfin/mach-bf533/Kconfig +++ /dev/null @@ -1,96 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if (BF533 || BF532 || BF531) - -source "arch/blackfin/mach-bf533/boards/Kconfig" - -menu "BF533/2/1 Specific Configuration" - -comment "Interrupt Priority Assignment" -menu "Priority" - -config UART_ERROR - int "UART ERROR" - default 7 -config SPORT0_ERROR - int "SPORT0 ERROR" - default 7 -config SPI_ERROR - int "SPI ERROR" - default 7 -config SPORT1_ERROR - int "SPORT1 ERROR" - default 7 -config PPI_ERROR - int "PPI ERROR" - default 7 -config DMA_ERROR - int "DMA ERROR" - default 7 -config PLLWAKE_ERROR - int "PLL WAKEUP ERROR" - default 7 - -config RTC_ERROR - int "RTC ERROR" - default 8 -config DMA0_PPI - int "DMA0 PPI" - default 8 - -config DMA1_SPORT0RX - int "DMA1 (SPORT0 RX)" - default 9 -config DMA2_SPORT0TX - int "DMA2 (SPORT0 TX)" - default 9 -config DMA3_SPORT1RX - int "DMA3 (SPORT1 RX)" - default 9 -config DMA4_SPORT1TX - int "DMA4 (SPORT1 TX)" - default 9 -config DMA5_SPI - int "DMA5 (SPI)" - default 10 -config DMA6_UARTRX - int "DMA6 (UART0 RX)" - default 10 -config DMA7_UARTTX - int "DMA7 (UART0 TX)" - default 10 -config TIMER0 - int "TIMER0" - default 7 if TICKSOURCE_GPTMR0 - default 8 -config TIMER1 - int "TIMER1" - default 11 -config TIMER2 - int "TIMER2" - default 11 -config PFA - int "PF Interrupt A" - default 12 -config PFB - int "PF Interrupt B" - default 12 -config MEMDMA0 - int "MEMORY DMA0" - default 13 -config MEMDMA1 - int "MEMORY DMA1" - default 13 -config WDTIMER - int "WATCH DOG TIMER" - default 13 - - help - Enter the priority numbers between 7-13 ONLY. Others are Reserved. - This applies to all the above. It is not recommended to assign the - highest priority number 7 to UART or any other device. - -endmenu - -endmenu - -endif diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile deleted file mode 100644 index 874840f76028..000000000000 --- a/arch/blackfin/mach-bf533/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# arch/blackfin/mach-bf533/Makefile -# - -obj-y := ints-priority.o dma.o diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c deleted file mode 100644 index 01300f40db15..000000000000 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2007-2008 HV Sistemas S.L. - * Javier Herrero <jherrero@hvsistemas.es> - * 2005 National ICT Australia (NICTA) - * Aidan Williams <aidan@nicta.com.au> - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include <linux/usb/isp1362.h> -#endif -#include <linux/irq.h> - -#include <asm/dma.h> -#include <asm/bfin5xx_spi.h> -#include <asm/reboot.h> -#include <asm/portmux.h> - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "HV Sistemas H8606"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* -* Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_DM9000) -static struct resource dm9000_resources[] = { - [0] = { - .start = 0x20300000, - .end = 0x20300002, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 0x20300004, - .end = 0x20300006, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | - IORESOURCE_IRQ_SHAREABLE), - }, -}; - -static struct platform_device dm9000_device = { - .id = 0, - .name = "dm9000", - .resource = dm9000_resources, - .num_resources = ARRAY_SIZE(dm9000_resources), -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include <linux/smc91x.h> - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PROG_INTB, - .end = IRQ_PROG_INTB, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader (spi)", - .size = 0x40000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "fpga (spi)", - .size = 0x30000, - .offset = 0x40000 - }, { - .name = "linux kernel (spi)", - .size = 0x150000, - .offset = 0x70000 - }, { - .name = "jffs2 root file system (spi)", - .size = 0x640000, - .offset = 0x1c0000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -/* Notice: for blackfin, the speed_hz is the value of register - * SPI_BAUD, not the real baudrate */ -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - /* this value is the baudrate divisor */ - .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 16, - .bus_num = 1, - .chip_select = 4, - }, -#endif - -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_8250) - -#include <linux/serial_8250.h> -#include <linux/serial.h> - -/* - * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010. - * running at half system clock, both with interrupt output or-ed to PF8. Change to - * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus - */ - -static struct plat_serial8250_port serial8250_platform_data [] = { - { - .membase = (void *)0x20200000, - .mapbase = 0x20200000, - .irq = IRQ_PF8, - .irqflags = IRQF_TRIGGER_HIGH, - .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, - .iotype = UPIO_MEM, - .regshift = 1, - .uartclk = 66666667, - }, { - .membase = (void *)0x20200010, - .mapbase = 0x20200010, - .irq = IRQ_PF8, - .irqflags = IRQF_TRIGGER_HIGH, - .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, - .iotype = UPIO_MEM, - .regshift = 1, - .uartclk = 66666667, - }, { - } -}; - -static struct platform_device serial8250_device = { - .id = PLAT8250_DEV_PLATFORM, - .name = "serial8250", - .dev = { - .platform_data = serial8250_platform_data, - }, -}; - -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES) - -/* - * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030, - * interrupt output wired to PF9. Change to suit different FPGA configuration - */ - -static struct resource opencores_kbd_resources[] = { - [0] = { - .start = 0x20200030, - .end = 0x20300030 + 2, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device opencores_kbd_device = { - .id = -1, - .name = "opencores-kbd", - .resource = opencores_kbd_resources, - .num_resources = ARRAY_SIZE(opencores_kbd_resources), -}; -#endif - -static struct platform_device *h8606_devices[] __initdata = { -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_8250) - &serial8250_device, -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES) - &opencores_kbd_device, -#endif -}; - -static int __init H8606_init(void) -{ - printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - return 0; -} - -arch_initcall(H8606_init); - -static struct platform_device *H8606_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(H8606_early_devices, - ARRAY_SIZE(H8606_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig deleted file mode 100644 index 3fde0df1b5f2..000000000000 --- a/arch/blackfin/mach-bf533/boards/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -choice - prompt "System type" - default BFIN533_STAMP - help - Select your board! - -config BFIN533_EZKIT - bool "BF533-EZKIT" - help - BF533-EZKIT-LITE board support. - -config BFIN533_STAMP - bool "BF533-STAMP" - help - BF533-STAMP board support. - -config BLACKSTAMP - bool "BlackStamp" - help - Support for the BlackStamp board. Hardware info available at - http://blackfin.uclinux.org/gf/project/blackstamp/ - -config BFIN533_BLUETECHNIX_CM - bool "Bluetechnix CM-BF533" - depends on (BF533) - help - CM-BF533 support for EVAL- and DEV-Board. - -config H8606_HVSISTEMAS - bool "HV Sistemas H8606" - depends on (BF532) - help - HV Sistemas H8606 board support. - -config BFIN532_IP0X - bool "IP04/IP08 IP-PBX" - depends on (BF532) - help - Core support for IP04/IP04 open hardware IP-PBX. - -endchoice diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile deleted file mode 100644 index 35256d2fc040..000000000000 --- a/arch/blackfin/mach-bf533/boards/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/blackfin/mach-bf533/boards/Makefile -# - -obj-$(CONFIG_BFIN533_STAMP) += stamp.o -obj-$(CONFIG_BFIN532_IP0X) += ip0x.o -obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o -obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o -obj-$(CONFIG_BLACKSTAMP) += blackstamp.o -obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c deleted file mode 100644 index fab69c736515..000000000000 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ /dev/null @@ -1,523 +0,0 @@ -/* - * Board Info File for the BlackStamp - * - * Copyright 2004-2008 Analog Devices Inc. - * 2008 Benjamin Matthews <bmat@lle.rochester.edu> - * 2005 National ICT Australia (NICTA) - * Aidan Williams <aidan@nicta.com.au> - * - * More info about the BlackStamp at: - * http://blackfin.uclinux.org/gf/project/blackstamp/ - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/gpio/machine.h> -#include <asm/dma.h> -#include <asm/bfin5xx_spi.h> -#include <asm/portmux.h> -#include <asm/dpmc.h> - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "BlackStamp"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include <linux/smc91x.h> - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF3, - .end = IRQ_PF3, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. */ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 7, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include <linux/input.h> -#include <linux/gpio_keys.h> - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF4, 0, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF5, 0, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF6, 0, "gpio-keys: BTN2"}, -}; /* Mapped to the first three PF Test Points */ - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include <linux/i2c-gpio.h> - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 40, -}; /* This hasn't actually been used these pins - * are (currently) free pins on the expansion connector */ - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -}; - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif -}; - -static int __init blackstamp_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - - ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - if (ret < 0) - return ret; - -#if IS_ENABLED(CONFIG_SMC91X) - /* - * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC. - * the bfin-async-map driver takes care of flipping between - * flash and ethernet when necessary. - */ - ret = gpio_request(GPIO_PF0, "enet_cpld"); - if (!ret) { - gpio_direction_output(GPIO_PF0, 1); - gpio_free(GPIO_PF0); - } -#endif - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(blackstamp_init); - -static struct platform_device *stamp_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(stamp_early_devices, - ARRAY_SIZE(stamp_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c deleted file mode 100644 index 4ef2fb0e48d5..000000000000 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2008-2009 Bluetechnix - * 2005 National ICT Australia (NICTA) - * Aidan Williams <aidan@nicta.com.au> - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include <linux/spi/mmc_spi.h> -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include <linux/usb/isp1362.h> -#endif -#include <linux/irq.h> -#include <asm/dma.h> -#include <asm/bfin5xx_spi.h> -#include <asm/portmux.h> -#include <asm/dpmc.h> - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Bluetechnix CM BF533"; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = 0x20000 - }, { - .name = "file system(spi)", - .size = 0x700000, - .offset = 0x00100000, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SMC91X) -#include <linux/smc91x.h> - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .start = 0x20200300, - .end = 0x20200300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF0, - .end = IRQ_PF0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) -#include <linux/smsc911x.h> - -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x20308000, - .end = 0x20308000 + 0xFF, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF8, - .end = IRQ_PF8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20308000, - .end = 0x20308000, - .flags = IORESOURCE_MEM, - }, { - .start = 0x20308004, - .end = 0x20308004, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF4, - .end = IRQ_PF4, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF6, - .end = IRQ_PF6, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - - - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition para_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux+rootfs(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data para_flash_data = { - .width = 2, - .parts = para_partitions, - .nr_parts = ARRAY_SIZE(para_partitions), -}; - -static struct resource para_flash_resource = { - .start = 0x20000000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device para_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = ¶_flash_data, - }, - .num_resources = 1, - .resource = ¶_flash_resource, -}; -#endif - - - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *cm_bf533_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_SMSC911X) - &smsc911x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - ¶_flash_device, -#endif -}; - -static int __init cm_bf533_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices)); -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); -#endif - return 0; -} - -arch_initcall(cm_bf533_init); - -static struct platform_device *cm_bf533_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(cm_bf533_early_devices, - ARRAY_SIZE(cm_bf533_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c deleted file mode 100644 index d64d270e9e62..000000000000 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams <aidan@nicta.com.au> - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/plat-ram.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include <linux/usb/isp1362.h> -#endif -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/gpio/machine.h> -#include <asm/dma.h> -#include <asm/bfin5xx_spi.h> -#include <asm/portmux.h> -#include <asm/dpmc.h> - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF533-EZKIT"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* - * USB-LAN EzExtender board - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include <linux/smc91x.h> - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20310300, - .end = 0x20310300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF9, - .end = IRQ_PF9, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) -static struct mtd_partition ezkit_partitions_a[] = { - { - .name = "bootloader(nor a)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor a)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data ezkit_flash_data_a = { - .width = 2, - .parts = ezkit_partitions_a, - .nr_parts = ARRAY_SIZE(ezkit_partitions_a), -}; - -static struct resource ezkit_flash_resource_a = { - .start = 0x20000000, - .end = 0x200fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device_a = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ezkit_flash_data_a, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource_a, -}; - -static struct mtd_partition ezkit_partitions_b[] = { - { - .name = "file system(nor b)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data ezkit_flash_data_b = { - .width = 2, - .parts = ezkit_partitions_b, - .nr_parts = ARRAY_SIZE(ezkit_partitions_b), -}; - -static struct resource ezkit_flash_resource_b = { - .start = 0x20100000, - .end = 0x201fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ezkit_flash_device_b = { - .name = "physmap-flash", - .id = 4, - .dev = { - .platform_data = &ezkit_flash_data_b, - }, - .num_resources = 1, - .resource = &ezkit_flash_resource_b, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_PLATRAM) -static struct platdata_mtd_ram sram_data_a = { - .mapname = "Flash A SRAM", - .bankwidth = 2, -}; - -static struct resource sram_resource_a = { - .start = 0x20240000, - .end = 0x2024ffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device sram_device_a = { - .name = "mtd-ram", - .id = 8, - .dev = { - .platform_data = &sram_data_a, - }, - .num_resources = 1, - .resource = &sram_resource_a, -}; - -static struct platdata_mtd_ram sram_data_b = { - .mapname = "Flash B SRAM", - .bankwidth = 2, -}; - -static struct resource sram_resource_b = { - .start = 0x202c0000, - .end = 0x202cffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device sram_device_b = { - .name = "mtd-ram", - .id = 9, - .dev = { - .platform_data = &sram_data_b, - }, - .num_resources = 1, - .resource = &sram_resource_b, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00020000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0xe0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) - { - .modalias = "ad183x", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - }, -#endif -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include <linux/input.h> -#include <linux/gpio_keys.h> - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"}, - {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include <linux/i2c-gpio.h> - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 40, -}; - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - /* TODO: add platform data here */ -}; -#endif - -static struct platform_device *ezkit_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_MTD_PHYSMAP) - &ezkit_flash_device_a, - &ezkit_flash_device_b, -#endif - -#if IS_ENABLED(CONFIG_MTD_PLATRAM) - &sram_device_a, - &sram_device_b, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97, -#endif -}; - -static int __init ezkit_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - return 0; -} - -arch_initcall(ezkit_init); - -static struct platform_device *ezkit_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ezkit_early_devices, - ARRAY_SIZE(ezkit_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c deleted file mode 100644 index 39c8e8547b82..000000000000 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2007 David Rowe - * 2006 Intratrade Ltd. - * Ivan Danov <idanov@gmail.com> - * 2005 National ICT Australia (NICTA) - * Aidan Williams <aidan@nicta.com.au> - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include <linux/usb/isp1362.h> -#endif -#include <asm/irq.h> -#include <asm/dma.h> -#include <asm/bfin5xx_spi.h> -#include <asm/portmux.h> - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "IP04/IP08"; - -/* - * Driver needs to know address, irq and flag pin. - */ -#if defined(CONFIG_BFIN532_IP0X) -#if IS_ENABLED(CONFIG_DM9000) - -#include <linux/dm9000.h> - -static struct resource dm9000_resource1[] = { - { - .start = 0x20100000, - .end = 0x20100000 + 1, - .flags = IORESOURCE_MEM - },{ - .start = 0x20100000 + 2, - .end = 0x20100000 + 3, - .flags = IORESOURCE_MEM - },{ - .start = IRQ_PF15, - .end = IRQ_PF15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE - } -}; - -static struct resource dm9000_resource2[] = { - { - .start = 0x20200000, - .end = 0x20200000 + 1, - .flags = IORESOURCE_MEM - },{ - .start = 0x20200000 + 2, - .end = 0x20200000 + 3, - .flags = IORESOURCE_MEM - },{ - .start = IRQ_PF14, - .end = IRQ_PF14, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE - } -}; - -/* -* for the moment we limit ourselves to 16bit IO until some -* better IO routines can be written and tested -*/ -static struct dm9000_plat_data dm9000_platdata1 = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device dm9000_device1 = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9000_resource1), - .resource = dm9000_resource1, - .dev = { - .platform_data = &dm9000_platdata1, - } -}; - -static struct dm9000_plat_data dm9000_platdata2 = { - .flags = DM9000_PLATF_16BITONLY, -}; - -static struct platform_device dm9000_device2 = { - .name = "dm9000", - .id = 1, - .num_resources = ARRAY_SIZE(dm9000_resource2), - .resource = dm9000_resource2, - .dev = { - .platform_data = &dm9000_platdata2, - } -}; - -#endif -#endif - - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* all SPI peripherals info goes here */ - -#if IS_ENABLED(CONFIG_MMC_SPI) -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, /* if 1 - block!!! */ -}; -#endif - -/* Notice: for blackfin, the speed_hz is the value of register - * SPI_BAUD, not the real baudrate */ -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 2, - .bus_num = 1, - .chip_select = 5, - .controller_data = &mmc_spi_chip_info, - }, -#endif -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master spi_bfin_master_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ -}; - -static struct platform_device spi_bfin_master_device = { - .name = "bfin-spi-master", - .id = 1, /* Bus number */ - .dev = { - .platform_data = &spi_bfin_master_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -static struct resource isp1362_hcd_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 1, - .flags = IORESOURCE_MEM, - },{ - .start = 0x20300000 + 2, - .end = 0x20300000 + 3, - .flags = IORESOURCE_MEM, - },{ - .start = IRQ_PF11, - .end = IRQ_PF11, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct isp1362_platform_data isp1362_priv = { - .sel15Kres = 1, - .clknotstop = 0, - .oc_enable = 0, /* external OC */ - .int_act_high = 0, - .int_edge_triggered = 0, - .remote_wakeup_connected = 0, - .no_power_switching = 1, - .power_switching_mode = 0, -}; - -static struct platform_device isp1362_hcd_device = { - .name = "isp1362-hcd", - .id = 0, - .dev = { - .platform_data = &isp1362_priv, - }, - .num_resources = ARRAY_SIZE(isp1362_hcd_resources), - .resource = isp1362_hcd_resources, -}; -#endif - - -static struct platform_device *ip0x_devices[] __initdata = { -#if defined(CONFIG_BFIN532_IP0X) -#if IS_ENABLED(CONFIG_DM9000) - &dm9000_device1, - &dm9000_device2, -#endif -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &spi_bfin_master_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) - &isp1362_hcd_device, -#endif -}; - -static int __init ip0x_init(void) -{ - printk(KERN_INFO "%s(): registering device resources\n", __func__); - platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - - return 0; -} - -arch_initcall(ip0x_init); - -static struct platform_device *ip0x_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(ip0x_early_devices, - ARRAY_SIZE(ip0x_early_devices)); -} diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c deleted file mode 100644 index 27cbf2fa2c62..000000000000 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ /dev/null @@ -1,919 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * 2005 National ICT Australia (NICTA) - * Aidan Williams <aidan@nicta.com.au> - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/device.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/spi/flash.h> -#include <linux/spi/mmc_spi.h> -#if IS_ENABLED(CONFIG_USB_ISP1362_HCD) -#include <linux/usb/isp1362.h> -#endif -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/gpio/machine.h> -#include <asm/dma.h> -#include <asm/bfin5xx_spi.h> -#include <asm/reboot.h> -#include <asm/portmux.h> -#include <asm/dpmc.h> - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "ADI BF533-STAMP"; - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) -static struct platform_device rtc_device = { - .name = "rtc-bfin", - .id = -1, -}; -#endif - -/* - * Driver needs to know address, irq and flag pin. - */ -#if IS_ENABLED(CONFIG_SMC91X) -#include <linux/smc91x.h> - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - { - .name = "smc91x-regs", - .start = 0x20300300, - .end = 0x20300300 + 16, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &smc91x_info, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) -static struct resource net2272_bfin_resources[] = { - { - .start = 0x20300000, - .end = 0x20300000 + 0x100, - .flags = IORESOURCE_MEM, - }, { - .start = 1, - .flags = IORESOURCE_BUS, - }, { - .start = IRQ_PF10, - .end = IRQ_PF10, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, - }, -}; - -static struct platform_device net2272_bfin_device = { - .name = "net2272", - .id = -1, - .num_resources = ARRAY_SIZE(net2272_bfin_resources), - .resource = net2272_bfin_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC) -static struct mtd_partition stamp_partitions[] = { - { - .name = "bootloader(nor)", - .size = 0x40000, - .offset = 0, - }, { - .name = "linux kernel(nor)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(nor)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct physmap_flash_data stamp_flash_data = { - .width = 2, - .parts = stamp_partitions, - .nr_parts = ARRAY_SIZE(stamp_partitions), -}; - -static struct resource stamp_flash_resource[] = { - { - .name = "cfi_probe", - .start = 0x20000000, - .end = 0x203fffff, - .flags = IORESOURCE_MEM, - }, { - .start = 0x7BB07BB0, /* AMBCTL0 setting when accessing flash */ - .end = 0x7BB07BB0, /* AMBCTL1 setting when accessing flash */ - .flags = IORESOURCE_MEM, - }, { - .start = GPIO_PF0, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device stamp_flash_device = { - .name = "bfin-async-flash", - .id = 0, - .dev = { - .platform_data = &stamp_flash_data, - }, - .num_resources = ARRAY_SIZE(stamp_flash_resource), - .resource = stamp_flash_resource, -}; -#endif - -#if IS_ENABLED(CONFIG_MTD_M25P80) -static struct mtd_partition bfin_spi_flash_partitions[] = { - { - .name = "bootloader(spi)", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_CAP_ROM - }, { - .name = "linux kernel(spi)", - .size = 0x180000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "file system(spi)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_flash_data = { - .name = "m25p80", - .parts = bfin_spi_flash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), - .type = "m25p64", -}; - -/* SPI flash chip (m25p64) */ -static struct bfin5xx_spi_chip spi_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_SPI) -#define MMC_SPI_CARD_DETECT_INT IRQ_PF5 -static int bfin_mmc_spi_init(struct device *dev, - irqreturn_t (*detect_int)(int, void *), void *data) -{ - return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "mmc-spi-detect", data); -} - -static void bfin_mmc_spi_exit(struct device *dev, void *data) -{ - free_irq(MMC_SPI_CARD_DETECT_INT, data); -} - -static struct mmc_spi_platform_data bfin_mmc_spi_pdata = { - .init = bfin_mmc_spi_init, - .exit = bfin_mmc_spi_exit, - .detect_delay = 100, /* msecs */ -}; - -static struct bfin5xx_spi_chip mmc_spi_chip_info = { - .enable_dma = 0, - .pio_interrupt = 0, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if IS_ENABLED(CONFIG_MTD_M25P80) - { - /* the modalias must be the same as spi device driver name */ - .modalias = "m25p80", /* Name of spi_driver for this device */ - .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ - .platform_data = &bfin_spi_flash_data, - .controller_data = &spi_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - { - .modalias = "ad1836", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = "ad1836", /* only includes chip name for the moment */ - .mode = SPI_MODE_3, - }, -#endif - -#if IS_ENABLED(CONFIG_SPI_SPIDEV) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 1, - }, -#endif -#if IS_ENABLED(CONFIG_MMC_SPI) - { - .modalias = "mmc_spi", - .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 4, - .platform_data = &bfin_mmc_spi_pdata, - .controller_data = &mmc_spi_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - } -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif /* spi master and devices */ - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL+2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_TX, - .end = IRQ_UART0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART0_ERROR, - .end = IRQ_UART0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_TX, - .end = CH_UART0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 -static struct resource bfin_sir0_resources[] = { - { - .start = 0xFFC00400, - .end = 0xFFC004FF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART0_RX, - .end = IRQ_UART0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART0_RX, - .end = CH_UART0_RX+1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device bfin_sir0_device = { - .name = "bfin_sir", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sir0_resources), - .resource = bfin_sir0_resources, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART -static struct resource bfin_sport0_uart_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport0_peripherals[] = { - P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, - P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 -}; - -static struct platform_device bfin_sport0_uart_device = { - .name = "bfin-sport-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), - .resource = bfin_sport0_uart_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ - }, -}; -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART -static struct resource bfin_sport1_uart_resources[] = { - { - .start = SPORT1_TCR1, - .end = SPORT1_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT1_RX, - .end = IRQ_SPORT1_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT1_ERROR, - .end = IRQ_SPORT1_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static unsigned short bfin_sport1_peripherals[] = { - P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, - P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 -}; - -static struct platform_device bfin_sport1_uart_device = { - .name = "bfin-sport-uart", - .id = 1, - .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), - .resource = bfin_sport1_uart_resources, - .dev = { - .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ - }, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SPORT) -static struct resource bfin_sport0_resources[] = { - { - .start = SPORT0_TCR1, - .end = SPORT0_MRCS3+4, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_SPORT0_TX, - .end = IRQ_SPORT0_TX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_RX, - .end = IRQ_SPORT0_RX+1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_SPORT0_ERROR, - .end = IRQ_SPORT0_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_SPORT0_TX, - .end = CH_SPORT0_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_SPORT0_RX, - .end = CH_SPORT0_RX, - .flags = IORESOURCE_DMA, - }, -}; -static struct platform_device bfin_sport0_device = { - .name = "bfin_sport_raw", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_sport0_resources), - .resource = bfin_sport0_resources, - .dev = { - .platform_data = &bfin_sport0_peripherals, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) -#include <linux/input.h> -#include <linux/gpio_keys.h> - -static struct gpio_keys_button bfin_gpio_keys_table[] = { - {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"}, - {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"}, - {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"}, -}; - -static struct gpio_keys_platform_data bfin_gpio_keys_data = { - .buttons = bfin_gpio_keys_table, - .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), -}; - -static struct platform_device bfin_device_gpiokeys = { - .name = "gpio-keys", - .dev = { - .platform_data = &bfin_gpio_keys_data, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) -#include <linux/i2c-gpio.h> - -static struct gpiod_lookup_table bfin_i2c_gpiod_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct i2c_gpio_platform_data i2c_gpio_data = { - .udelay = 10, -}; - -static struct platform_device i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &i2c_gpio_data, - }, -}; -#endif - -static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if IS_ENABLED(CONFIG_JOYSTICK_AD7142) - { - I2C_BOARD_INFO("ad7142_joystick", 0x2C), - .irq = 39, - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("pcf8574_lcd", 0x22), - }, -#endif -#if IS_ENABLED(CONFIG_INPUT_PCF8574) - { - I2C_BOARD_INFO("pcf8574_keypad", 0x27), - .irq = 39, - }, -#endif -#if IS_ENABLED(CONFIG_FB_BFIN_7393) - { - I2C_BOARD_INFO("bfin-adv7393", 0x2B), - }, -#endif -#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) - { - I2C_BOARD_INFO("ad5252", 0x2f), - }, -#endif -}; - -static const unsigned int cclk_vlev_datasheet[] = -{ - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 376000000), - VRPAIR(VLEV_095, 426000000), - VRPAIR(VLEV_100, 426000000), - VRPAIR(VLEV_105, 476000000), - VRPAIR(VLEV_110, 476000000), - VRPAIR(VLEV_115, 476000000), - VRPAIR(VLEV_120, 600000000), - VRPAIR(VLEV_125, 600000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */, -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \ - IS_ENABLED(CONFIG_SND_BF5XX_AC97) - -#include <asm/bfin_sport.h> - -#define SPORT_REQ(x) \ - [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ - P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} - -static const u16 bfin_snd_pin[][7] = { - SPORT_REQ(0), - SPORT_REQ(1), -}; - -static struct bfin_snd_platform_data bfin_snd_data[] = { - { - .pin_req = &bfin_snd_pin[0][0], - }, - { - .pin_req = &bfin_snd_pin[1][0], - }, -}; - -#define BFIN_SND_RES(x) \ - [x] = { \ - { \ - .start = SPORT##x##_TCR1, \ - .end = SPORT##x##_TCR1, \ - .flags = IORESOURCE_MEM \ - }, \ - { \ - .start = CH_SPORT##x##_RX, \ - .end = CH_SPORT##x##_RX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = CH_SPORT##x##_TX, \ - .end = CH_SPORT##x##_TX, \ - .flags = IORESOURCE_DMA, \ - }, \ - { \ - .start = IRQ_SPORT##x##_ERROR, \ - .end = IRQ_SPORT##x##_ERROR, \ - .flags = IORESOURCE_IRQ, \ - } \ - } - -static struct resource bfin_snd_resources[][4] = { - BFIN_SND_RES(0), - BFIN_SND_RES(1), -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) -static struct platform_device bfin_i2s_pcm = { - .name = "bfin-i2s-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) -static struct platform_device bfin_ac97_pcm = { - .name = "bfin-ac97-pcm-audio", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) -static const char * const ad1836_link[] = { - "bfin-i2s.0", - "spi0.4", -}; -static struct platform_device bfin_ad1836_machine = { - .name = "bfin-snd-ad1836", - .id = -1, - .dev = { - .platform_data = (void *)ad1836_link, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) -static const unsigned ad73311_gpio[] = { - GPIO_PF4, -}; - -static struct platform_device bfin_ad73311_machine = { - .name = "bfin-snd-ad73311", - .id = 1, - .dev = { - .platform_data = (void *)ad73311_gpio, - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD73311) -static struct platform_device bfin_ad73311_codec_device = { - .name = "ad73311", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD74111) -static struct platform_device bfin_ad74111_codec_device = { - .name = "ad74111", - .id = -1, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) -static struct platform_device bfin_i2s = { - .name = "bfin-i2s", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = - ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) -static struct platform_device bfin_ac97 = { - .name = "bfin-ac97", - .id = CONFIG_SND_BF5XX_SPORT_NUM, - .num_resources = - ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), - .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], - .dev = { - .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], - }, -}; -#endif - -static struct platform_device *stamp_devices[] __initdata = { - - &bfin_dpmc, - -#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) - &rtc_device, -#endif - -#if IS_ENABLED(CONFIG_SMC91X) - &smc91x_device, -#endif - -#if IS_ENABLED(CONFIG_USB_NET2272) - &net2272_bfin_device, -#endif - -#if IS_ENABLED(CONFIG_SPI_BFIN5XX) - &bfin_spi0_device, -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_BFIN_SIR) -#ifdef CONFIG_BFIN_SIR0 - &bfin_sir0_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif - -#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) - &bfin_device_gpiokeys, -#endif - -#if IS_ENABLED(CONFIG_I2C_GPIO) - &i2c_gpio_device, -#endif - -#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC) - &stamp_flash_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) - &bfin_i2s_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) - &bfin_ac97_pcm, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836) - &bfin_ad1836_machine, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) - &bfin_ad73311_machine, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD73311) - &bfin_ad73311_codec_device, -#endif - -#if IS_ENABLED(CONFIG_SND_SOC_AD74111) - &bfin_ad74111_codec_device, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) - &bfin_i2s, -#endif - -#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) - &bfin_ac97, -#endif -}; - -static int __init net2272_init(void) -{ -#if IS_ENABLED(CONFIG_USB_NET2272) - int ret; - - /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */ - ret = gpio_request(GPIO_PF0, "net2272"); - if (ret) - return ret; - - ret = gpio_request(GPIO_PF1, "net2272"); - if (ret) { - gpio_free(GPIO_PF0); - return ret; - } - - ret = gpio_request(GPIO_PF11, "net2272"); - if (ret) { - gpio_free(GPIO_PF0); - gpio_free(GPIO_PF1); - return ret; - } - - gpio_direction_output(GPIO_PF0, 0); - gpio_direction_output(GPIO_PF1, 1); - - /* Reset the USB chip */ - gpio_direction_output(GPIO_PF11, 0); - mdelay(2); - gpio_set_value(GPIO_PF11, 1); -#endif - - return 0; -} - -static int __init stamp_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - -#if IS_ENABLED(CONFIG_I2C_GPIO) - gpiod_add_lookup_table(&bfin_i2c_gpiod_table); -#endif - i2c_register_board_info(0, bfin_i2c_board_info, - ARRAY_SIZE(bfin_i2c_board_info)); - - ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); - if (ret < 0) - return ret; - -#if IS_ENABLED(CONFIG_SMC91X) - /* - * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC. - * the bfin-async-map driver takes care of flipping between - * flash and ethernet when necessary. - */ - ret = gpio_request(GPIO_PF0, "enet_cpld"); - if (!ret) { - gpio_direction_output(GPIO_PF0, 1); - gpio_free(GPIO_PF0); - } -#endif - - if (net2272_init()) - pr_warning("unable to configure net2272; it probably won't work\n"); - - spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(stamp_init); - -static struct platform_device *stamp_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - -#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) -#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART - &bfin_sport0_uart_device, -#endif -#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART - &bfin_sport1_uart_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(stamp_early_devices, - ARRAY_SIZE(stamp_early_devices)); -} - -void native_machine_restart(char *cmd) -{ - /* workaround pull up on cpld / flash pin not being strong enough */ - gpio_request(GPIO_PF0, "flash_cpld"); - gpio_direction_output(GPIO_PF0, 0); -} diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c deleted file mode 100644 index 1f5988d43139..000000000000 --- a/arch/blackfin/mach-bf533/dma.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * simple DMA Implementation for Blackfin - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/module.h> - -#include <asm/blackfin.h> -#include <asm/dma.h> - -struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { - (struct dma_register *) DMA0_NEXT_DESC_PTR, - (struct dma_register *) DMA1_NEXT_DESC_PTR, - (struct dma_register *) DMA2_NEXT_DESC_PTR, - (struct dma_register *) DMA3_NEXT_DESC_PTR, - (struct dma_register *) DMA4_NEXT_DESC_PTR, - (struct dma_register *) DMA5_NEXT_DESC_PTR, - (struct dma_register *) DMA6_NEXT_DESC_PTR, - (struct dma_register *) DMA7_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, - (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, - (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, -}; -EXPORT_SYMBOL(dma_io_base_addr); - -int channel2irq(unsigned int channel) -{ - int ret_irq = -1; - - switch (channel) { - case CH_PPI: - ret_irq = IRQ_PPI; - break; - - case CH_SPORT0_RX: - ret_irq = IRQ_SPORT0_RX; - break; - - case CH_SPORT0_TX: - ret_irq = IRQ_SPORT0_TX; - break; - - case CH_SPORT1_RX: - ret_irq = IRQ_SPORT1_RX; - break; - - case CH_SPORT1_TX: - ret_irq = IRQ_SPORT1_TX; - break; - - case CH_SPI: - ret_irq = IRQ_SPI; - break; - - case CH_UART0_RX: - ret_irq = IRQ_UART0_RX; - break; - - case CH_UART0_TX: - ret_irq = IRQ_UART0_TX; - break; - - case CH_MEM_STREAM0_SRC: - case CH_MEM_STREAM0_DEST: - ret_irq = IRQ_MEM_DMA0; - break; - - case CH_MEM_STREAM1_SRC: - case CH_MEM_STREAM1_DEST: - ret_irq = IRQ_MEM_DMA1; - break; - } - return ret_irq; -} diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h deleted file mode 100644 index 0e754efc3cf6..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ /dev/null @@ -1,383 +0,0 @@ -/* - * DO NOT EDIT THIS FILE - * This file is under version control at - * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ - * and can be replaced with that version at any time - * DO NOT EDIT THIS FILE - * - * Copyright 2004-2011 Analog Devices Inc. - * Licensed under the Clear BSD license. - */ - -/* This file should be up to date with: - * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List - */ - -#ifndef _MACH_ANOMALY_H_ -#define _MACH_ANOMALY_H_ - -/* We do not support 0.1 or 0.2 silicon - sorry */ -#if __SILICON_REVISION__ < 3 -# error will not work on BF533 silicon version 0.0, 0.1, or 0.2 -#endif - -#if defined(__ADSPBF531__) -# define ANOMALY_BF531 1 -#else -# define ANOMALY_BF531 0 -#endif -#if defined(__ADSPBF532__) -# define ANOMALY_BF532 1 -#else -# define ANOMALY_BF532 0 -#endif -#if defined(__ADSPBF533__) -# define ANOMALY_BF533 1 -#else -# define ANOMALY_BF533 0 -#endif - -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ -#define ANOMALY_05000074 (1) -/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ -#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ -#define ANOMALY_05000105 (__SILICON_REVISION__ > 2) -/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) -/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ -#define ANOMALY_05000122 (1) -/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ -#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) -/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ -#define ANOMALY_05000166 (1) -/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ -#define ANOMALY_05000167 (1) -/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ -#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) -/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ -#define ANOMALY_05000180 (1) -/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ -#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) -/* False Protection Exceptions when Speculative Fetch Is Cancelled */ -#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) -/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ -#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) -/* Restarting SPORT in Specific Modes May Cause Data Corruption */ -#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) -/* Failing MMR Accesses when Preceding Memory Read Stalls */ -#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) -/* Current DMA Address Shows Wrong Value During Carry Fix */ -#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) -/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ -#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) -/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ -#define ANOMALY_05000201 (__SILICON_REVISION__ == 3) -/* Possible Infinite Stall with Specific Dual-DAG Situation */ -#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) -/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ -#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) -/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ -#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) -/* Recovery from "Brown-Out" Condition */ -#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) -/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */ -#define ANOMALY_05000208 (1) -/* Speed Path in Computational Unit Affects Certain Instructions */ -#define ANOMALY_05000209 (__SILICON_REVISION__ < 4) -/* UART TX Interrupt Masked Erroneously */ -#define ANOMALY_05000215 (__SILICON_REVISION__ < 5) -/* NMI Event at Boot Time Results in Unpredictable State */ -#define ANOMALY_05000219 (1) -/* Incorrect Pulse-Width of UART Start Bit */ -#define ANOMALY_05000225 (__SILICON_REVISION__ < 5) -/* Scratchpad Memory Bank Reads May Return Incorrect Data */ -#define ANOMALY_05000227 (__SILICON_REVISION__ < 5) -/* SPI Slave Boot Mode Modifies Registers from Reset Value */ -#define ANOMALY_05000229 (1) -/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */ -#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) -/* UART STB Bit Incorrectly Affects Receiver Setting */ -#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) -/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) -/* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000234 (__SILICON_REVISION__ == 4) -/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ -#define ANOMALY_05000245 (1) -/* Data CPLBs Should Prevent False Hardware Errors */ -#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) -/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ -#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) -/* Maximum External Clock Speed for Timers */ -#define ANOMALY_05000253 (__SILICON_REVISION__ < 5) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ -#define ANOMALY_05000254 (__SILICON_REVISION__ > 4) -/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ -#define ANOMALY_05000255 (__SILICON_REVISION__ < 5) -/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ -#define ANOMALY_05000257 (__SILICON_REVISION__ < 5) -/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ -#define ANOMALY_05000258 (__SILICON_REVISION__ < 5) -/* ICPLB_STATUS MMR Register May Be Corrupted */ -#define ANOMALY_05000260 (__SILICON_REVISION__ < 5) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 5) -/* Stores To Data Cache May Be Lost */ -#define ANOMALY_05000262 (__SILICON_REVISION__ < 5) -/* Hardware Loop Corrupted When Taking an ICPLB Exception */ -#define ANOMALY_05000263 (__SILICON_REVISION__ < 5) -/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ -#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) -/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (1) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ -#define ANOMALY_05000269 (__SILICON_REVISION__ < 5) -/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ -#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) -/* Spontaneous Reset of Internal Voltage Regulator */ -#define ANOMALY_05000271 (__SILICON_REVISION__ == 3) -/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) -/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ -#define ANOMALY_05000276 (1) -/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) -/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) -/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) -/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ -#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) -/* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) -/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) -/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ -#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) -/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ -#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) -/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ -#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) -/* SCKELOW Bit Does Not Maintain State Through Hibernate */ -#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ -/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ -#define ANOMALY_05000310 (1) -/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ -#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) -/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ -#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) -/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ -#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) -/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ -#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) -/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) -/* UART Break Signal Issues */ -#define ANOMALY_05000363 (__SILICON_REVISION__ < 5) -/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ -#define ANOMALY_05000366 (1) -/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) -/* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) -/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ -#define ANOMALY_05000403 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) -/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ -#define ANOMALY_05000426 (1) -/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ -#define ANOMALY_05000443 (1) -/* False Hardware Error when RETI Points to Invalid Memory */ -#define ANOMALY_05000461 (1) -/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ -#define ANOMALY_05000471 (1) -/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ -#define ANOMALY_05000473 (1) -/* Possible Lockup Condition when Modifying PLL from External Memory */ -#define ANOMALY_05000475 (1) -/* TESTSET Instruction Cannot Be Interrupted */ -#define ANOMALY_05000477 (1) -/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ -#define ANOMALY_05000481 (1) -/* PLL May Latch Incorrect Values Coming Out of Reset */ -#define ANOMALY_05000489 (1) -/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ -#define ANOMALY_05000491 (1) -/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ -#define ANOMALY_05000494 (1) -/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ -#define ANOMALY_05000501 (1) - -/* - * These anomalies have been "phased" out of analog.com anomaly sheets and are - * here to show running on older silicon just isn't feasible. - */ - -/* Internal voltage regulator can't be modified via register writes */ -#define ANOMALY_05000066 (__SILICON_REVISION__ < 2) -/* Watchpoints (Hardware Breakpoints) are not supported */ -#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) -/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ -#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) -/* Writing FIO_DIR can corrupt a programmable flag's data */ -#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) -/* Timer Auto-Baud Mode requires the UART clock to be enabled. */ -#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) -/* Internal Clocking Modes on SPORT0 not supported */ -#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) -/* Internal voltage regulator does not wake up from an RTC wakeup */ -#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) -/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ -#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) -/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ -#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) -/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ -#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) -/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ -#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) -/* 32-bit SPORT DMA will be word reversed */ -#define ANOMALY_05000098 (__SILICON_REVISION__ < 2) -/* Incorrect status in the UART_IIR register */ -#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) -/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ -#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) -/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ -#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) -/* Incorrect Value Written to the Cycle Counters */ -#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) -/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ -#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) -/* Programmable Flag (PF3) functionality not supported in all PPI modes */ -#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) -/* Data store can be lost when targeting a cache line fill */ -#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) -/* Reserved Bits in SYSCFG Register Not Set at Power-On */ -#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) -/* Infinite Core Stall */ -#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) -/* PPI_FSx may glitch when generated by the on chip Timers. */ -#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) -/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) -/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ -#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) -/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ -#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) -/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ -#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) -/* Erroneous Exception when Enabling Cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) -/* SPI clock polarity and phase bits incorrect during booting */ -#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> Is Not Set on Reset */ -#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) -/* SPI boot will not complete if there is a zero fill block in the loader file */ -#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) -/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ -#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000143 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) -/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ -#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) -/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ -#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) -/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ -#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) -/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ -#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) -/* Cache Fill Buffer Data lost */ -#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) -/* Overlapping Sequencer and Memory Stalls */ -#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) -/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ -#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) -/* Disabling the PPI Resets the PPI Configuration Registers */ -#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) -/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ -#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) -/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ -#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) -/* Internal Voltage Regulator may not start up */ -#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) - -/* Anomalies that don't exist on this proc */ -#define ANOMALY_05000120 (0) -#define ANOMALY_05000149 (0) -#define ANOMALY_05000171 (0) -#define ANOMALY_05000182 (0) -#define ANOMALY_05000220 (0) -#define ANOMALY_05000248 (0) -#define ANOMALY_05000266 (0) -#define ANOMALY_05000274 (0) -#define ANOMALY_05000287 (0) -#define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) -#define ANOMALY_05000362 (1) -#define ANOMALY_05000364 (0) -#define ANOMALY_05000380 (0) -#define ANOMALY_05000383 (0) -#define ANOMALY_05000386 (1) -#define ANOMALY_05000389 (0) -#define ANOMALY_05000412 (0) -#define ANOMALY_05000430 (0) -#define ANOMALY_05000432 (0) -#define ANOMALY_05000435 (0) -#define ANOMALY_05000440 (0) -#define ANOMALY_05000447 (0) -#define ANOMALY_05000448 (0) -#define ANOMALY_05000456 (0) -#define ANOMALY_05000450 (0) -#define ANOMALY_05000465 (0) -#define ANOMALY_05000467 (0) -#define ANOMALY_05000474 (0) -#define ANOMALY_05000480 (0) -#define ANOMALY_05000485 (0) -#define ANOMALY_16000030 (0) - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h deleted file mode 100644 index e3e05f8f7af9..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/bf533.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 - * - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __MACH_BF533_H__ -#define __MACH_BF533_H__ - -#define OFFSET_(x) ((x) & 0x0000FFFF) - -/*some misc defines*/ -#define IMASK_IVG15 0x8000 -#define IMASK_IVG14 0x4000 -#define IMASK_IVG13 0x2000 -#define IMASK_IVG12 0x1000 - -#define IMASK_IVG11 0x0800 -#define IMASK_IVG10 0x0400 -#define IMASK_IVG9 0x0200 -#define IMASK_IVG8 0x0100 - -#define IMASK_IVG7 0x0080 -#define IMASK_IVGTMR 0x0040 -#define IMASK_IVGHW 0x0020 - -/***************************/ - - -#define BFIN_DSUBBANKS 4 -#define BFIN_DWAYS 2 -#define BFIN_DLINES 64 -#define BFIN_ISUBBANKS 4 -#define BFIN_IWAYS 4 -#define BFIN_ILINES 32 - -#define WAY0_L 0x1 -#define WAY1_L 0x2 -#define WAY01_L 0x3 -#define WAY2_L 0x4 -#define WAY02_L 0x5 -#define WAY12_L 0x6 -#define WAY012_L 0x7 - -#define WAY3_L 0x8 -#define WAY03_L 0x9 -#define WAY13_L 0xA -#define WAY013_L 0xB - -#define WAY32_L 0xC -#define WAY320_L 0xD -#define WAY321_L 0xE -#define WAYALL_L 0xF - -#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ - -/* IAR0 BIT FIELDS*/ -#define RTC_ERROR_BIT 0x0FFFFFFF -#define UART_ERROR_BIT 0xF0FFFFFF -#define SPORT1_ERROR_BIT 0xFF0FFFFF -#define SPI_ERROR_BIT 0xFFF0FFFF -#define SPORT0_ERROR_BIT 0xFFFF0FFF -#define PPI_ERROR_BIT 0xFFFFF0FF -#define DMA_ERROR_BIT 0xFFFFFF0F -#define PLLWAKE_ERROR_BIT 0xFFFFFFFF - -/* IAR1 BIT FIELDS*/ -#define DMA7_UARTTX_BIT 0x0FFFFFFF -#define DMA6_UARTRX_BIT 0xF0FFFFFF -#define DMA5_SPI_BIT 0xFF0FFFFF -#define DMA4_SPORT1TX_BIT 0xFFF0FFFF -#define DMA3_SPORT1RX_BIT 0xFFFF0FFF -#define DMA2_SPORT0TX_BIT 0xFFFFF0FF -#define DMA1_SPORT0RX_BIT 0xFFFFFF0F -#define DMA0_PPI_BIT 0xFFFFFFFF - -/* IAR2 BIT FIELDS*/ -#define WDTIMER_BIT 0x0FFFFFFF -#define MEMDMA1_BIT 0xF0FFFFFF -#define MEMDMA0_BIT 0xFF0FFFFF -#define PFB_BIT 0xFFF0FFFF -#define PFA_BIT 0xFFFF0FFF -#define TIMER2_BIT 0xFFFFF0FF -#define TIMER1_BIT 0xFFFFFF0F -#define TIMER0_BIT 0xFFFFFFFF - -/********************************* EBIU Settings ************************************/ -#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) -#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) - -#ifdef CONFIG_C_AMBEN_ALL -#define V_AMBEN AMBEN_ALL -#endif -#ifdef CONFIG_C_AMBEN -#define V_AMBEN 0x0 -#endif -#ifdef CONFIG_C_AMBEN_B0 -#define V_AMBEN AMBEN_B0 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1 -#define V_AMBEN AMBEN_B0_B1 -#endif -#ifdef CONFIG_C_AMBEN_B0_B1_B2 -#define V_AMBEN AMBEN_B0_B1_B2 -#endif -#ifdef CONFIG_C_AMCKEN -#define V_AMCKEN AMCKEN -#else -#define V_AMCKEN 0x0 -#endif -#ifdef CONFIG_C_CDPRIO -#define V_CDPRIO 0x100 -#else -#define V_CDPRIO 0x0 -#endif - -#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) - -#ifdef CONFIG_BF533 -#define CPU "BF533" -#define CPUID 0x27a5 -#endif -#ifdef CONFIG_BF532 -#define CPU "BF532" -#define CPUID 0x27a5 -#endif -#ifdef CONFIG_BF531 -#define CPU "BF531" -#define CPUID 0x27a5 -#endif - -#ifndef CPU -#error "Unknown CPU type - This kernel doesn't seem to be configured properly" -#endif - -#endif /* __MACH_BF533_H__ */ diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h deleted file mode 100644 index 08072c86d5dc..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * mach/bfin_serial.h - Blackfin UART/Serial definitions - * - * Copyright 2006-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_SERIAL_H__ -#define __BFIN_MACH_SERIAL_H__ - -#define BFIN_UART_NR_PORTS 1 - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h deleted file mode 100644 index e366207fbf12..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_BLACKFIN_H_ -#define _MACH_BLACKFIN_H_ - -#define BF533_FAMILY - -#include "bf533.h" -#include "anomaly.h" - -#include <asm/def_LPBlackfin.h> -#include "defBF532.h" - -#ifndef __ASSEMBLY__ -# include <asm/cdef_LPBlackfin.h> -# include "cdefBF532.h" -#endif - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h deleted file mode 100644 index fd0cbe4df21a..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ /dev/null @@ -1,682 +0,0 @@ -/* - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _CDEF_BF532_H -#define _CDEF_BF532_H - -/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) - -/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST,val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) - -/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) - -/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) -#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) -#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) - -/* DMA Traffic controls */ -#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) -#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) -#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) -#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) - -/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ -#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) -#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) -#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) -#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) -#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) -#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val) -#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) -#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val) -#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) -#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val) -#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) -#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val) -#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) -#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val) -#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) -#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) -#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) -#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) -#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) -#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) -#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) -#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val) -#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) -#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val) -#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) -#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) - -#if ANOMALY_05000311 -/* Keep at the CPP expansion to avoid circular header dependency loops */ -#define BFIN_WRITE_FIO_FLAG(name, val) \ - do { \ - unsigned long __flags; \ - __flags = hard_local_irq_save(); \ - bfin_write16(FIO_FLAG_##name, val); \ - bfin_read_CHIPID(); \ - hard_local_irq_restore(__flags); \ - } while (0) -#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) -#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) -#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) -#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) - -#define BFIN_READ_FIO_FLAG(name) \ - ({ \ - unsigned long __flags; \ - u16 __ret; \ - __flags = hard_local_irq_save(); \ - __ret = bfin_read16(FIO_FLAG_##name); \ - bfin_read_CHIPID(); \ - hard_local_irq_restore(__flags); \ - __ret; \ - }) -#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) -#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) -#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) -#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) - -#else -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#endif - -/* DMA Controller */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) - -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) - -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) - -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) - -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) - -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) - -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) - -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) - -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) - -/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) - -/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) - -/* UART Controller */ -#define bfin_read_UART_THR() bfin_read16(UART_THR) -#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) -#define bfin_read_UART_RBR() bfin_read16(UART_RBR) -#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) -#define bfin_read_UART_DLL() bfin_read16(UART_DLL) -#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) -#define bfin_read_UART_IER() bfin_read16(UART_IER) -#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) -#define bfin_read_UART_DLH() bfin_read16(UART_DLH) -#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) -#define bfin_read_UART_IIR() bfin_read16(UART_IIR) -#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) -#define bfin_read_UART_LCR() bfin_read16(UART_LCR) -#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) -#define bfin_read_UART_MCR() bfin_read16(UART_MCR) -#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) -#define bfin_read_UART_LSR() bfin_read16(UART_LSR) -#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) -/* -#define UART_MSR -*/ -#define bfin_read_UART_SCR() bfin_read16(UART_SCR) -#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) -#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) -#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) - -/* SPI Controller */ -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) - -/* TIMER 0, 1, 2 Registers */ -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) - -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) - -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) - -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) -#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val) - -/* SPORT0 Controller */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) - -/* SPORT1 Controller */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) - -/* Parallel Peripheral Interface (PPI) */ -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) -#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) - -#endif /* _CDEF_BF532_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h deleted file mode 100644 index d438150b1025..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ /dev/null @@ -1,831 +0,0 @@ -/* - * System & MMR bit and Address definitions for ADSP-BF532 - * - * Copyright 2005-2010 Analog Devices Inc. - * - * Licensed under the Clear BSD license or the GPL-2 (or later) - */ - -#ifndef _DEF_BF532_H -#define _DEF_BF532_H - -/*********************************************************************************** */ -/* System MMR Register Map */ -/*********************************************************************************** */ -/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ - -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define CHIPID 0xFFC00014 /* Chip ID Register */ - -/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration registe */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ - -/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ - -/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ - -/* UART Controller (0xFFC00400 - 0xFFC004FF) */ - -/* - * Because include/linux/serial_reg.h have defined UART_*, - * So we define blackfin uart regs to BFIN_UART_*. - */ -#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ -#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ -#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ -#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ -#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ -#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ -#if 0 -#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ -#endif -#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ -#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ - -/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ -#define SPI0_REGBASE 0xFFC00500 -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ - -/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ - -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ - -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ - -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ - -#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ - -/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ - -#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ -#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ -#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ -#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ -#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ -#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ -#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ -#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ -#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ -#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ -#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ -#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ -#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ -#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ -#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ -#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ -#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ - -/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ - -/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ - -/* Asynchronous Memory Controller - External Bus Interface Unit */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ - -/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ - -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ - -/* DMA Traffic controls */ -#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ -#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ - -/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ - -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ - -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ - -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ - -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ - -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ - -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ - -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ - -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ - -#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ - -#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ - -#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ - -/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ - -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ - -/*********************************************************************************** */ -/* System MMR Register Bits */ -/******************************************************************************* */ - -/* CHIPID Masks */ -#define CHIPID_VERSION 0xF0000000 -#define CHIPID_FAMILY 0x0FFFF000 -#define CHIPID_MANUFACTURE 0x00000FFE - -/* SWRST Mask */ -#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ -#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ -#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ -#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ -#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ - -/* SYSCR Masks */ -#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ -#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ - -/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ - - /* SIC_IAR0 Masks */ - -#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ -#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ -#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ -#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ -#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ -#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ -#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ -#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ - -/* SIC_IAR1 Masks */ - -#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ -#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ -#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ -#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ -#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ -#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ -#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ -#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ - -/* SIC_IAR2 Masks */ -#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ -#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ -#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ -#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ -#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ -#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ -#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ -#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ - -/* SIC_IMASK Masks */ -#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ -#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ -#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ -#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ - -/* SIC_IWR Masks */ -#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ -#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ -#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ -#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ - -/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ - -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 /* PPI Port Enable */ -#define PORT_DIR 0x00000002 /* PPI Port Direction */ -#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ -#define PORT_CFG 0x00000030 /* PPI Port Configuration */ -#define FLD_SEL 0x00000040 /* PPI Active Field Select */ -#define PACK_EN 0x00000080 /* PPI Packing Mode */ -#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ -#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ -#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ -#define DLENGTH 0x00003800 /* PPI Data Length */ -#define DLEN_8 0x0000 /* Data Length = 8 Bits */ -#define DLEN_10 0x0800 /* Data Length = 10 Bits */ -#define DLEN_11 0x1000 /* Data Length = 11 Bits */ -#define DLEN_12 0x1800 /* Data Length = 12 Bits */ -#define DLEN_13 0x2000 /* Data Length = 13 Bits */ -#define DLEN_14 0x2800 /* Data Length = 14 Bits */ -#define DLEN_15 0x3000 /* Data Length = 15 Bits */ -#define DLEN_16 0x3800 /* Data Length = 16 Bits */ -#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ -#define POL 0x0000C000 /* PPI Signal Polarities */ -#define POLC 0x4000 /* PPI Clock Polarity */ -#define POLS 0x8000 /* PPI Frame Sync Polarity */ - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 /* Field Indicator */ -#define FT_ERR 0x00000800 /* Frame Track Error */ -#define OVR 0x00001000 /* FIFO Overflow Error */ -#define UNDR 0x00002000 /* FIFO Underrun Error */ -#define ERR_DET 0x00004000 /* Error Detected Indicator */ -#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ - -/* ********** DMA CONTROLLER MASKS *********************8 */ - -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ - -#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ -#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ -#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ -#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ -#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ -#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ -#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ -#define PMAP 0x00007000 /* DMA Peripheral Map Field */ - -#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ -#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ -#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ -#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ -#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ -#define PMAP_SPI 0x5000 /* PMAP SPI DMA */ -#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */ -#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */ - -/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ - -/* PWM Timer bit definitions */ - -/* TIMER_ENABLE Register */ -#define TIMEN0 0x0001 -#define TIMEN1 0x0002 -#define TIMEN2 0x0004 - -#define TIMEN0_P 0x00 -#define TIMEN1_P 0x01 -#define TIMEN2_P 0x02 - -/* TIMER_DISABLE Register */ -#define TIMDIS0 0x0001 -#define TIMDIS1 0x0002 -#define TIMDIS2 0x0004 - -#define TIMDIS0_P 0x00 -#define TIMDIS1_P 0x01 -#define TIMDIS2_P 0x02 - -/* TIMER_STATUS Register */ -#define TIMIL0 0x0001 -#define TIMIL1 0x0002 -#define TIMIL2 0x0004 -#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ -#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ -#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ -#define TRUN0 0x1000 -#define TRUN1 0x2000 -#define TRUN2 0x4000 - -#define TIMIL0_P 0x00 -#define TIMIL1_P 0x01 -#define TIMIL2_P 0x02 -#define TOVF_ERR0_P 0x04 -#define TOVF_ERR1_P 0x05 -#define TOVF_ERR2_P 0x06 -#define TRUN0_P 0x0C -#define TRUN1_P 0x0D -#define TRUN2_P 0x0E - -/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ -#define TOVL_ERR0 TOVF_ERR0 -#define TOVL_ERR1 TOVF_ERR1 -#define TOVL_ERR2 TOVF_ERR2 -#define TOVL_ERR0_P TOVF_ERR0_P -#define TOVL_ERR1_P TOVF_ERR1_P -#define TOVL_ERR2_P TOVF_ERR2_P - -/* TIMERx_CONFIG Registers */ -#define PWM_OUT 0x0001 -#define WDTH_CAP 0x0002 -#define EXT_CLK 0x0003 -#define PULSE_HI 0x0004 -#define PERIOD_CNT 0x0008 -#define IRQ_ENA 0x0010 -#define TIN_SEL 0x0020 -#define OUT_DIS 0x0040 -#define CLK_SEL 0x0080 -#define TOGGLE_HI 0x0100 -#define EMU_RUN 0x0200 -#define ERR_TYP(x) ((x & 0x03) << 14) - -#define TMODE_P0 0x00 -#define TMODE_P1 0x01 -#define PULSE_HI_P 0x02 -#define PERIOD_CNT_P 0x03 -#define IRQ_ENA_P 0x04 -#define TIN_SEL_P 0x05 -#define OUT_DIS_P 0x06 -#define CLK_SEL_P 0x07 -#define TOGGLE_HI_P 0x08 -#define EMU_RUN_P 0x09 -#define ERR_TYP_P0 0x0E -#define ERR_TYP_P1 0x0F - -/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ - -/* AMGCTL Masks */ -#define AMCKEN 0x00000001 /* Enable CLKOUT */ -#define AMBEN_NONE 0x00000000 /* All Banks Disabled */ -#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ -#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ -#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ -#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ - -/* AMGCTL Bit Positions */ -#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ -#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ -#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ -#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ - -/* AMBCTL0 Masks */ -#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ -#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ -#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ -#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ -#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ -#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ -#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ -#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ -#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ -#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ -#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ -#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ -#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ -#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ -#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ -#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ -#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ -#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ -#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ -#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ -#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ -#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ -#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ -#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ -#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ -#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ -#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ -#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ -#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ -#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ -#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ -#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ -#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ -#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ -#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ -#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ -#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ -#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ -#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ -#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ -#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ -#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ -#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ -#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ -#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ -#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ -#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ -#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ -#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ -#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ -#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ -#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ -#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ -#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ -#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ -#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ -#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ -#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ -#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ -#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ -#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ -#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ -#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ -#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ -#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ -#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ -#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ -#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ -#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ -#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ -#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ -#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ -#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ -#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ -#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ -#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ -#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ -#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ -#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ -#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ - -/* AMBCTL1 Masks */ -#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ -#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ -#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ -#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ -#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ -#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ -#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ -#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ -#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ -#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ -#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ -#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ -#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ -#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ -#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ -#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ -#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ -#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ -#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ -#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ -#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ -#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ -#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ -#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ -#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ -#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ -#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ -#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ -#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ -#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ -#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ -#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ -#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ -#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ -#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ -#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ -#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ -#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ -#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ -#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ -#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ -#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ -#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ -#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ -#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ -#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ -#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ -#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ -#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ -#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ -#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ -#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ -#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ -#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ -#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ -#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ -#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ -#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ -#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ -#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ -#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ -#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ -#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ -#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ -#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ -#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ -#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ -#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ -#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ -#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ -#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ -#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ -#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ -#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ -#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ -#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ -#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ -#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ -#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ -#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ - -/* ********************** SDRAM CONTROLLER MASKS *************************** */ - -/* SDGCTL Masks */ -#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ -#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ -#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ -#define PFE 0x00000010 /* Enable SDRAM prefetch */ -#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ -#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ -#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ -#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ -#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ -#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ -#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ -#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ -#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ -#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ -#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ -#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ -#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ -#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ -#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ -#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ -#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ -#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ -#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ -#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ -#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ -#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ -#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ -#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ -#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ -#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ -#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ -#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ -#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ -#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ -#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ -#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ -#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ -#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ -#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ -#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ -#define PUPSD 0x00200000 /*Power-up start delay */ -#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ -#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ -#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ -#define EBUFE 0x02000000 /* Enable external buffering timing */ -#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ -#define EMREN 0x10000000 /* Extended mode register enable */ -#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ -#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ - -/* EBIU_SDBCTL Masks */ -#define EBE 0x00000001 /* Enable SDRAM external bank */ -#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ -#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ -#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ -#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ -#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ -#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ -#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ - -/* EBIU_SDSTAT Masks */ -#define SDCI 0x00000001 /* SDRAM controller is idle */ -#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ -#define SDPUA 0x00000004 /* SDRAM power up active */ -#define SDRS 0x00000008 /* SDRAM is in reset state */ -#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ -#define BGSTAT 0x00000020 /* Bus granted */ - - -#endif /* _DEF_BF532_H */ diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h deleted file mode 100644 index fb34934c5ba8..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/dma.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mach/dma.h - arch-specific DMA defines - * - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _MACH_DMA_H_ -#define _MACH_DMA_H_ - -#define MAX_DMA_CHANNELS 12 - -#define CH_PPI 0 -#define CH_SPORT0_RX 1 -#define CH_SPORT0_TX 2 -#define CH_SPORT1_RX 3 -#define CH_SPORT1_TX 4 -#define CH_SPI 5 -#define CH_UART0_RX 6 -#define CH_UART0_TX 7 -#define CH_MEM_STREAM0_DEST 8 /* TX */ -#define CH_MEM_STREAM0_SRC 9 /* RX */ -#define CH_MEM_STREAM1_DEST 10 /* TX */ -#define CH_MEM_STREAM1_SRC 11 /* RX */ - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h deleted file mode 100644 index cce4f8fb3785..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/gpio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2008 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - - -#ifndef _MACH_GPIO_H_ -#define _MACH_GPIO_H_ - -#define MAX_BLACKFIN_GPIOS 16 - -#define GPIO_PF0 0 -#define GPIO_PF1 1 -#define GPIO_PF2 2 -#define GPIO_PF3 3 -#define GPIO_PF4 4 -#define GPIO_PF5 5 -#define GPIO_PF6 6 -#define GPIO_PF7 7 -#define GPIO_PF8 8 -#define GPIO_PF9 9 -#define GPIO_PF10 10 -#define GPIO_PF11 11 -#define GPIO_PF12 12 -#define GPIO_PF13 13 -#define GPIO_PF14 14 -#define GPIO_PF15 15 - -#define PORT_F GPIO_PF0 - -#include <mach-common/ports-f.h> - -#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h deleted file mode 100644 index 709733754142..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/irq.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2005-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _BF533_IRQ_H_ -#define _BF533_IRQ_H_ - -#include <mach-common/irq.h> - -#define NR_PERI_INTS 24 - -#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ -#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ -#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */ -#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ -#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ -#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */ -#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */ -#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ -#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */ -#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */ -#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */ -#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */ -#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */ -#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */ -#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */ -#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */ -#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */ -#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */ -#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */ -#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */ -#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */ -#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */ -#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */ - -#define SYS_IRQS 31 - -#define IRQ_PF0 33 -#define IRQ_PF1 34 -#define IRQ_PF2 35 -#define IRQ_PF3 36 -#define IRQ_PF4 37 -#define IRQ_PF5 38 -#define IRQ_PF6 39 -#define IRQ_PF7 40 -#define IRQ_PF8 41 -#define IRQ_PF9 42 -#define IRQ_PF10 43 -#define IRQ_PF11 44 -#define IRQ_PF12 45 -#define IRQ_PF13 46 -#define IRQ_PF14 47 -#define IRQ_PF15 48 - -#define GPIO_IRQ_BASE IRQ_PF0 - -#define NR_MACH_IRQS (IRQ_PF15 + 1) - -/* IAR0 BIT FIELDS */ -#define RTC_ERROR_POS 28 -#define UART_ERROR_POS 24 -#define SPORT1_ERROR_POS 20 -#define SPI_ERROR_POS 16 -#define SPORT0_ERROR_POS 12 -#define PPI_ERROR_POS 8 -#define DMA_ERROR_POS 4 -#define PLLWAKE_ERROR_POS 0 - -/* IAR1 BIT FIELDS */ -#define DMA7_UARTTX_POS 28 -#define DMA6_UARTRX_POS 24 -#define DMA5_SPI_POS 20 -#define DMA4_SPORT1TX_POS 16 -#define DMA3_SPORT1RX_POS 12 -#define DMA2_SPORT0TX_POS 8 -#define DMA1_SPORT0RX_POS 4 -#define DMA0_PPI_POS 0 - -/* IAR2 BIT FIELDS */ -#define WDTIMER_POS 28 -#define MEMDMA1_POS 24 -#define MEMDMA0_POS 20 -#define PFB_POS 16 -#define PFA_POS 12 -#define TIMER2_POS 8 -#define TIMER1_POS 4 -#define TIMER0_POS 0 - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h deleted file mode 100644 index 197af1a398ac..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/mem_map.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * BF533 memory map - * - * Copyright 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_MACH_MEM_MAP_H__ -#define __BFIN_MACH_MEM_MAP_H__ - -#ifndef __BFIN_MEM_MAP_H__ -# error "do not include mach/mem_map.h directly -- use asm/mem_map.h" -#endif - -/* Async Memory Banks */ -#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ -#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ -#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ -#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ -#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ -#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ - -/* Boot ROM Memory */ - -#define BOOT_ROM_START 0xEF000000 -#define BOOT_ROM_LENGTH 0x400 - -/* Level 1 Memory */ - -#ifdef CONFIG_BFIN_ICACHE -#define BFIN_ICACHESIZE (16*1024) -#else -#define BFIN_ICACHESIZE (0*1024) -#endif - -/* Memory Map for ADSP-BF533 processors */ - -#ifdef CONFIG_BF533 -#define L1_CODE_START 0xFFA00000 -#define L1_DATA_A_START 0xFF800000 -#define L1_DATA_B_START 0xFF900000 - -#ifdef CONFIG_BFIN_ICACHE -#define L1_CODE_LENGTH (0x14000 - 0x4000) -#else -#define L1_CODE_LENGTH 0x14000 -#endif - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x8000 - 0x4000) -#define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x8000 -#define L1_DATA_B_LENGTH 0x8000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ -#endif - -/* Memory Map for ADSP-BF532 processors */ - -#ifdef CONFIG_BF532 -#define L1_CODE_START 0xFFA08000 -#define L1_DATA_A_START 0xFF804000 -#define L1_DATA_B_START 0xFF904000 - -#ifdef CONFIG_BFIN_ICACHE -#define L1_CODE_LENGTH (0xC000 - 0x4000) -#else -#define L1_CODE_LENGTH 0xC000 -#endif - -#ifdef CONFIG_BFIN_DCACHE - -#ifdef CONFIG_BFIN_DCACHE_BANKA -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define L1_DATA_B_LENGTH 0x4000 -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 - -#else -#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BFIN_DCACHESIZE (32*1024) -#define BFIN_DSUPBANKS 2 -#endif - -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x4000 -#define L1_DATA_B_LENGTH 0x4000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif /*CONFIG_BFIN_DCACHE*/ -#endif - -/* Memory Map for ADSP-BF531 processors */ - -#ifdef CONFIG_BF531 -#define L1_CODE_START 0xFFA08000 -#define L1_DATA_A_START 0xFF804000 -#define L1_DATA_B_START 0xFF904000 -#define L1_CODE_LENGTH 0x4000 -#define L1_DATA_B_LENGTH 0x0000 - - -#ifdef CONFIG_BFIN_DCACHE -#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define BFIN_DCACHESIZE (16*1024) -#define BFIN_DSUPBANKS 1 -#else -#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) -#define L1_DATA_A_LENGTH 0x4000 -#define BFIN_DCACHESIZE (0*1024) -#define BFIN_DSUPBANKS 0 -#endif - -#endif - -#endif diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h deleted file mode 100644 index 94cca674d835..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/pll.h +++ /dev/null @@ -1 +0,0 @@ -#include <mach-common/pll.h> diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h deleted file mode 100644 index 96f5d9129f20..000000000000 --- a/arch/blackfin/mach-bf533/include/mach/portmux.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#ifndef _MACH_PORTMUX_H_ -#define _MACH_PORTMUX_H_ - -#define MAX_RESOURCES MAX_BLACKFIN_GPIOS - -#define P_PPI0_CLK (P_DONTCARE) -#define P_PPI0_FS1 (P_DONTCARE) -#define P_PPI0_FS2 (P_DONTCARE) -#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) -#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) -#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) -#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) -#define P_PPI0_D0 (P_DONTCARE) -#define P_PPI0_D1 (P_DONTCARE) -#define P_PPI0_D2 (P_DONTCARE) -#define P_PPI0_D3 (P_DONTCARE) -#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) -#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) -#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) -#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) - -#define P_SPORT1_TSCLK (P_DONTCARE) -#define P_SPORT1_RSCLK (P_DONTCARE) -#define P_SPORT0_TSCLK (P_DONTCARE) -#define P_SPORT0_RSCLK (P_DONTCARE) -#define P_UART0_RX (P_DONTCARE) -#define P_UART0_TX (P_DONTCARE) -#define P_SPORT1_DRSEC (P_DONTCARE) -#define P_SPORT1_RFS (P_DONTCARE) -#define P_SPORT1_DTPRI (P_DONTCARE) -#define P_SPORT1_DTSEC (P_DONTCARE) -#define P_SPORT1_TFS (P_DONTCARE) -#define P_SPORT1_DRPRI (P_DONTCARE) -#define P_SPORT0_DRSEC (P_DONTCARE) -#define P_SPORT0_RFS (P_DONTCARE) -#define P_SPORT0_DTPRI (P_DONTCARE) -#define P_SPORT0_DTSEC (P_DONTCARE) -#define P_SPORT0_TFS (P_DONTCARE) -#define P_SPORT0_DRPRI (P_DONTCARE) - -#define P_SPI0_MOSI (P_DONTCARE) -#define P_SPI0_MISO (P_DONTCARE) -#define P_SPI0_SCK (P_DONTCARE) -#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) -#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) -#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) -#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) -#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) -#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) -#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) -#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 -#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 - -#define P_TMR2 (P_DONTCARE) -#define P_TMR1 (P_DONTCARE) -#define P_TMR0 (P_DONTCARE) -#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) - -#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c deleted file mode 100644 index 8f714cf8135b..000000000000 --- a/arch/blackfin/mach-bf533/ints-priority.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <linux/module.h> -#include <linux/irq.h> -#include <asm/blackfin.h> - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) | - ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) | - ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) | - ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) | - ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) | - ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) | - ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) | - ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS)); - - bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) | - ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) | - ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) | - ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) | - ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) | - ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) | - ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) | - ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS)); - - bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) | - ((CONFIG_TIMER1 - 7) << TIMER1_POS) | - ((CONFIG_TIMER2 - 7) << TIMER2_POS) | - ((CONFIG_PFA - 7) << PFA_POS) | - ((CONFIG_PFB - 7) << PFB_POS) | - ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) | - ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) | - ((CONFIG_WDTIMER - 7) << WDTIMER_POS)); - - SSYNC(); -} |