diff options
| author | Guo Ren <guoren@linux.alibaba.com> | 2020-09-07 06:20:18 +0000 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 09:52:40 +0800 |
| commit | 0c8a32eed1625a65798286fb73fea8710a908545 (patch) | |
| tree | 69992b6e217f5e985ebbf1f739b2af336d89138c /arch/csky/include/asm/pgalloc.h | |
| parent | 7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff) | |
csky: Add memory layout 2.5G(user):1.5G(kernel)
There are two ways for translating va to pa for csky:
- Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
- Use SSEG0/1 (Simple Segment Mapping)
We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/include/asm/pgalloc.h')
| -rw-r--r-- | arch/csky/include/asm/pgalloc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/csky/include/asm/pgalloc.h b/arch/csky/include/asm/pgalloc.h index d58d8146b729..33878c4aaa60 100644 --- a/arch/csky/include/asm/pgalloc.h +++ b/arch/csky/include/asm/pgalloc.h @@ -71,7 +71,7 @@ do { \ } while (0) extern void pagetable_init(void); -extern void pre_mmu_init(void); +extern void mmu_init(unsigned long min_pfn, unsigned long max_pfn); extern void pre_trap_init(void); #endif /* __ASM_CSKY_PGALLOC_H */ |