diff options
| author | Guo Ren <guoren@linux.alibaba.com> | 2020-12-24 00:12:06 +0000 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 09:52:40 +0800 |
| commit | 7b513cf2bfdcdb7ba3f2b6e83f0e17e0793825d7 (patch) | |
| tree | fc41dd4b7048e1b566c1184cf063e40c42cea941 /arch/csky/include | |
| parent | 8e35ac734fe2a1a225143d6375f9678f1850585c (diff) | |
csky: Fixup PTE global for 2.5:1.5 virtual memory
Fixup commit c2d1adfa9a24 "csky: Add memory layout 2.5G(user):1.5G
(kernel)". That patch broke the global bit in PTE.
C-SKY TLB's entry contain two pages:
vpn, vpn + 1 -> ppn0, ppn1
All PPN's attributes contain global bit and final global is PPN0.G
& PPN1.G. So we must keep PPN0.G and PPN1.G same in one TLB's
entry.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/include')
| -rw-r--r-- | arch/csky/include/asm/pgtable.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/csky/include/asm/pgtable.h b/arch/csky/include/asm/pgtable.h index 6ec97af0d1ff..2485db84dba8 100644 --- a/arch/csky/include/asm/pgtable.h +++ b/arch/csky/include/asm/pgtable.h @@ -34,7 +34,7 @@ #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) #define pte_clear(mm, addr, ptep) set_pte((ptep), \ - (((unsigned int) addr & PAGE_OFFSET) ? __pte(_PAGE_GLOBAL) : __pte(0))) + (((unsigned int) addr >= PAGE_OFFSET) ? __pte(_PAGE_GLOBAL) : __pte(0))) #define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL)) #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) #define pte_pfn(x) ((unsigned long)((x).pte_low >> PAGE_SHIFT)) |