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authorGuo Ren <guoren@linux.alibaba.com>2020-09-07 06:20:18 +0000
committerGuo Ren <guoren@linux.alibaba.com>2021-01-12 09:52:40 +0800
commit0c8a32eed1625a65798286fb73fea8710a908545 (patch)
tree69992b6e217f5e985ebbf1f739b2af336d89138c /arch/csky/kernel/atomic.S
parent7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff)
csky: Add memory layout 2.5G(user):1.5G(kernel)
There are two ways for translating va to pa for csky: - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk) - Use SSEG0/1 (Simple Segment Mapping) We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1 are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0 to use 2G-2.5G as TLB user mapping. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/kernel/atomic.S')
-rw-r--r--arch/csky/kernel/atomic.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/csky/kernel/atomic.S b/arch/csky/kernel/atomic.S
index 3821ef9b7567..f03db1d8d060 100644
--- a/arch/csky/kernel/atomic.S
+++ b/arch/csky/kernel/atomic.S
@@ -14,6 +14,10 @@
*/
ENTRY(csky_cmpxchg)
USPTOKSP
+
+ RD_MEH a3
+ WR_MEH a3
+
mfcr a3, epc
addi a3, TRAP0_SIZE