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authorWill Deacon <will.deacon@arm.com>2013-09-03 19:10:11 +0100
committerWill Deacon <will.deacon@arm.com>2014-10-20 18:49:17 +0100
commitf6b3b7a9fa44ffa01f9c4f5ed13a9c48921e1ff2 (patch)
tree427de36817a19ed210a3c9ee28fdc5b8ed8388e6 /arch/ia64
parent62e8abf7161b6a0dd32752cd7c60237988f8bff7 (diff)
ia64: io: implement dummy relaxed accessor macros for writes
write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to ia64, which may be able to be optimised in a similar manner to the relaxed read accessors at a later date. Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/include/asm/io.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
index bee0acd52f7e..80a7e34be009 100644
--- a/arch/ia64/include/asm/io.h
+++ b/arch/ia64/include/asm/io.h
@@ -393,6 +393,10 @@ __writeq (unsigned long val, volatile void __iomem *addr)
#define writew(v,a) __writew((v), (a))
#define writel(v,a) __writel((v), (a))
#define writeq(v,a) __writeq((v), (a))
+#define writeb_relaxed(v,a) __writeb((v), (a))
+#define writew_relaxed(v,a) __writew((v), (a))
+#define writel_relaxed(v,a) __writel((v), (a))
+#define writeq_relaxed(v,a) __writeq((v), (a))
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel