diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-10 15:22:19 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:20 +1000 |
| commit | 07ffee59a756e3d16295fa1e0a4849c7a2273a13 (patch) | |
| tree | 07161a81e704f140d1cccd424d9f99df5490908b /arch/m68k/include/asm/cacheflush_no.h | |
| parent | 4a5bae416562a8224707a1ff30e83ddab1474fb3 (diff) | |
m68knommu: create optimal separate instruction and data cache for ColdFire
Create separate functions to deal with instruction and data cache flushing.
This way we can optimize them for the vairous cache types and arrangements
used across the ColdFire family.
For example the unified caches in the version 3 cores means we don't
need to flush the instruction cache. For the version 2 cores that do
not do data cacheing (or where we choose instruction cache only) we
don't need to do any data flushing.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/cacheflush_no.h')
| -rw-r--r-- | arch/m68k/include/asm/cacheflush_no.h | 38 |
1 files changed, 34 insertions, 4 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index f931e1829835..cb88aa96c4f1 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -12,14 +12,12 @@ #define flush_cache_dup_mm(mm) do { } while (0) #define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) -#ifndef flush_dcache_range -#define flush_dcache_range(start,len) __flush_cache_all() -#endif +#define flush_dcache_range(start, len) __flush_dcache_all() #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 #define flush_dcache_page(page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start,len) __flush_cache_all() +#define flush_icache_range(start, len) __flush_icache_all() #define flush_icache_page(vma,pg) do { } while (0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) @@ -46,4 +44,36 @@ static inline void __flush_cache_all(void) #endif } +/* + * Some ColdFire parts implement separate instruction and data caches, + * on those we should just flush the appropriate cache. If we don't need + * to do any specific flushing then this will be optimized away. + */ +static inline void __flush_icache_all(void) +{ +#ifdef CACHE_INVALIDATEI + __asm__ __volatile__ ( + "movel %0, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : "i" (CACHE_INVALIDATEI) : "d0" ); +#endif +} + +static inline void __flush_dcache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif +#ifdef CACHE_INVALIDATED + __asm__ __volatile__ ( + "movel %0, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : "i" (CACHE_INVALIDATED) : "d0" ); +#else + /* Flush the wrtite buffer */ + __asm__ __volatile__ ( "nop" ); +#endif +} #endif /* _M68KNOMMU_CACHEFLUSH_H */ |