diff options
| author | Michal Simek <monstr@monstr.eu> | 2010-02-04 11:42:24 +0100 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2010-03-11 14:08:55 +0100 |
| commit | 137d0795a72786fa33e6900cb2ac2eae81f4b6ee (patch) | |
| tree | 71b95d3a4e4d926b19b5ef28822eb784571475b7 /arch/microblaze/kernel/head.S | |
| parent | d79f3b06a9e40b382bd5d5ae8dea9b3210eda9ce (diff) | |
microblaze: Change temp register for cmdline
For copy was used r7 register when CONFIG_CMDLINE_BOOL option
is enabled. But r7 stores pointer to fdt that's why machine_early_init
not detect compiled-in DTB.
I also moved kernel PID setup to have TLB init in one block
Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze/kernel/head.S')
| -rw-r--r-- | arch/microblaze/kernel/head.S | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S index 30916193fcc7..cb7815cfe5ab 100644 --- a/arch/microblaze/kernel/head.S +++ b/arch/microblaze/kernel/head.S @@ -99,8 +99,8 @@ no_fdt_arg: tophys(r4,r4) /* convert to phys address */ ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ _copy_command_line: - lbu r7, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */ - sb r7, r4, r6 /* addr[r4+r6]= r7*/ + lbu r2, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */ + sb r2, r4, r6 /* addr[r4+r6]= r7*/ addik r6, r6, 1 /* increment counting */ bgtid r3, _copy_command_line /* loop for all entries */ addik r3, r3, -1 /* descrement loop */ @@ -136,6 +136,11 @@ _invalidate: addik r3, r3, -1 /* sync */ + /* Setup the kernel PID */ + mts rpid,r0 /* Load the kernel PID */ + nop + bri 4 + /* * We should still be executing code at physical address area * RAM_BASEADDR at this point. However, kernel code is at @@ -146,10 +151,6 @@ _invalidate: addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ tophys(r4,r3) /* Load the kernel physical address */ - mts rpid,r0 /* Load the kernel PID */ - nop - bri 4 - /* * Configure and load two entries into TLB slots 0 and 1. * In case we are pinning TLBs, these are reserved in by the |