diff options
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:45 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:23:48 +0200 |
| commit | 44def3426e4ac5a2dbdb5c8304397f4daa38eb2f (patch) | |
| tree | 365e80bb0639308afa9500270f69b83fdd6f0d3b /arch/mips/Kconfig | |
| parent | 5e5b6527128cea50f12a7064bf61b130b3a2739a (diff) | |
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 714cd81a779c..e4198c5c2aa8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -640,6 +640,7 @@ config SGI_IP22 select SYS_SUPPORTS_BIG_ENDIAN select WAR_R4600_V1_INDEX_ICACHEOP select WAR_R4600_V1_HIT_CACHEOP + select WAR_R4600_V2_HIT_CACHEOP select MIPS_L1_CACHE_SHIFT_7 help This are the SGI Indy, Challenge S and Indigo2, as well as certain @@ -877,6 +878,7 @@ config SNI_RM select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN + select WAR_R4600_V2_HIT_CACHEOP help The SNI RM200/300/400 are MIPS-based machines manufactured by Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid @@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP config WAR_R4600_V1_HIT_CACHEOP bool +# Writeback and invalidate the primary cache dcache before DMA. +# +# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, +# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only +# operate correctly if the internal data cache refill buffer is empty. These +# CACHE instructions should be separated from any potential data cache miss +# by a load instruction to an uncached address to empty the response buffer." +# (Revision 2.0 device errata from IDT available on https://www.idt.com/ +# in .pdf format.) +config WAR_R4600_V2_HIT_CACHEOP + bool + # # - Highmem only makes sense for the 32-bit kernel. # - The current highmem code will only work properly on physically indexed |