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authorManuel Lauss <manuel.lauss@googlemail.com>2011-11-02 12:53:44 +0100
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 22:02:05 +0000
commit3f724080a3e91d76ba6d5cacd3cf0a0cf16d121a (patch)
tree5e5b5606bd4822b6b8a4a0f1ef87332b7874af47 /arch/mips/alchemy/common/irq.c
parent5611cc4572e889b62a7b4c72a413536bf6a9c416 (diff)
MIPS: Alchemy: remove PB1000 support
Noone seems to have test hardware or care anymore. Drop PB1000 support and along with it the old Alchemy PCMCIA socket driver. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: linux-pcmcia@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/2881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/common/irq.c')
-rw-r--r--arch/mips/alchemy/common/irq.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b60ba0675e2..2a94a64b7333 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -35,9 +35,6 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mach-au1x00/au1000.h>
-#ifdef CONFIG_MIPS_PB1000
-#include <asm/mach-pb1x00/pb1000.h>
-#endif
/* Interrupt Controller register offsets */
#define IC_CFG0RD 0x40
@@ -265,14 +262,6 @@ static void au1x_ic1_unmask(struct irq_data *d)
__raw_writel(1 << bit, base + IC_MASKSET);
__raw_writel(1 << bit, base + IC_WAKESET);
-
-/* very hacky. does the pb1000 cpld auto-disable this int?
- * nowhere in the current kernel sources is it disabled. --mlau
- */
-#if defined(CONFIG_MIPS_PB1000)
- if (d->irq == AU1000_GPIO15_INT)
- __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
-#endif
wmb();
}