diff options
| author | Arınç ÜNAL <arinc.unal@arinc9.com> | 2023-02-11 13:49:15 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-02-17 11:58:37 +0100 |
| commit | bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b (patch) | |
| tree | ecea91381b3dc8241ea9007d3064ca632097c384 /arch/mips/ar7/time.c | |
| parent | 09e61efd884ca68a768717d60858f138685b161b (diff) | |
mips: dts: ralink: mt7621: add port@5 as CPU port
On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.
There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/ar7/time.c')
0 files changed, 0 insertions, 0 deletions