diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2023-12-12 17:34:33 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-12-21 15:30:03 +0100 |
| commit | f99c37d562250cbceed262723f91944c981eeb7b (patch) | |
| tree | e5967cbfabbb6481e970de159b9523f5e220d9fa /arch/mips/boot/compressed | |
| parent | 01940cd4a6b9c47995a0cdaaafdd459b0d2221a2 (diff) | |
MIPS: compressed: Use correct instruction for 64 bit code
The code clearing BSS already use macro or use correct instruction
depending if the CPU is 32 bits or 64 bits. However, a few
instructions remained 32 bits only.
By using the accurate MACRO, it is now possible to deal with memory
address beyond 32 bits. As a side effect, when using 64bits processor,
it also divides the loop number needed to clear the BSS by 2.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot/compressed')
| -rw-r--r-- | arch/mips/boot/compressed/head.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S index 5795d0af1e1b..d237a834b85e 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -25,8 +25,8 @@ /* Clear BSS */ PTR_LA a0, _edata PTR_LA a2, _end -1: sw zero, 0(a0) - addiu a0, a0, 4 +1: PTR_S zero, 0(a0) + PTR_ADDIU a0, a0, PTRSIZE bne a2, a0, 1b PTR_LA a0, (.heap) /* heap address */ |