summaryrefslogtreecommitdiff
path: root/arch/mips/boot/dts/ingenic/gcw0.dts
diff options
context:
space:
mode:
authorPaul Cercueil <paul@crapouillou.net>2018-01-16 16:48:04 +0100
committerJames Hogan <jhogan@kernel.org>2018-01-18 22:08:10 +0000
commit590c1f0f04336b92c802b94e2506efec5f6735f6 (patch)
treeac82f0ddf1208c1ad2f707e74f50e3655b0bd6d1 /arch/mips/boot/dts/ingenic/gcw0.dts
parentdec8cd4d9b9fa7dc0b7f253ebb31f2c3ef4213ac (diff)
MIPS: ingenic: Initial GCW Zero support
The GCW Zero (http://www.gcw-zero.com) is a retro-gaming focused handheld game console, successfully kickstarted in ~2012, running Linux. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Mathieu Malaterre <malat@debian.org> Acked-by: Philippe Ombredanne <pombredanne@nexb.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18490/ Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips/boot/dts/ingenic/gcw0.dts')
-rw-r--r--arch/mips/boot/dts/ingenic/gcw0.dts62
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
new file mode 100644
index 000000000000..35f0291e8d38
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/gcw0.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "jz4770.dtsi"
+
+/ {
+ compatible = "gcw,zero", "ingenic,jz4770";
+ model = "GCW Zero";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial2:57600n8";
+ };
+
+ board {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ otg_phy: otg-phy {
+ compatible = "usb-nop-xceiv";
+ clocks = <&cgu JZ4770_CLK_OTG_PHY>;
+ clock-names = "main_clk";
+ };
+ };
+};
+
+&ext {
+ clock-frequency = <12000000>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&cgu {
+ /* Put high-speed peripherals under PLL1, such that we can change the
+ * PLL0 frequency on demand without having to suspend peripherals.
+ * We use a rate of 432 MHz, which is the least common multiple of
+ * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
+ */
+ assigned-clocks =
+ <&cgu JZ4770_CLK_PLL1>,
+ <&cgu JZ4770_CLK_UHC>;
+ assigned-clock-parents =
+ <0>,
+ <&cgu JZ4770_CLK_PLL1>;
+ assigned-clock-rates =
+ <432000000>;
+};
+
+&uhc {
+ /* The WiFi module is connected to the UHC. */
+ status = "okay";
+};