diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2023-06-04 16:56:39 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-06-09 09:55:38 +0200 |
| commit | 868b70b9e6bd8d211cb846ad332c777591b68c8f (patch) | |
| tree | 87111053822ccf9effa127914eca5606a70113d0 /arch/mips/boot | |
| parent | 5fe60d3b680106109fd5c8b5270ef83f076b0c65 (diff) | |
MIPS: DTS: CI20: Parent MSCMUX clock to MPLL
This makes it possible to clock the SD cards much higher, as the MPLL is
running at 1.2 GHz by default. The previous parent was the EXT clock,
which caused the SD cards to be clocked at 24 MHz maximum.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot')
| -rw-r--r-- | arch/mips/boot/dts/ingenic/ci20.dts | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index b7dbafa1f85d..bdbd064c90e1 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -129,10 +129,11 @@ */ assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>, - <&cgu JZ4780_CLK_HDMI>; + <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>; assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>, <&cgu JZ4780_CLK_MPLL>, - <&cgu JZ4780_CLK_SSIPLL>; + <&cgu JZ4780_CLK_SSIPLL>, + <0>, <&cgu JZ4780_CLK_MPLL>; assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>; }; |