diff options
| author | James Hogan <james.hogan@imgtec.com> | 2016-05-11 13:50:51 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:30:25 +0200 |
| commit | e06a1548f3043febb658b58ec5ccbc7d03a785af (patch) | |
| tree | 4bf416b2262006e60bd3b81c24d089c03f5f3e37 /arch/mips/include/asm/cpu-features.h | |
| parent | 37fb60f8e3f011c25c120081a73886ad8dbc42fd (diff) | |
MIPS: Add defs & probing of BadInstr[P] registers
The optional CP0_BadInstr and CP0_BadInstrP registers are written with
the encoding of the instruction that caused a synchronous exception to
occur, and the prior branch instruction if in a delay slot.
These will be useful for instruction emulation in KVM, and especially
for VZ support where reading guest virtual memory is a bit more awkward.
Add CPU option numbers and cpu_has_* definitions to indicate the
presence of each registers, and add code to probe for them using bits in
the CP0_Config3 register.
[ralf@linux-mips.org: resolve merge conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13224/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 676a37b9c37e..5d82b01ef8b5 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -442,4 +442,12 @@ # define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG) #endif +#ifndef cpu_has_badinstr +# define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR) +#endif + +#ifndef cpu_has_badinstrp +# define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP) +#endif + #endif /* __ASM_CPU_FEATURES_H */ |