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authorChristoph Hellwig <hch@lst.de>2018-06-15 13:08:31 +0200
committerPaul Burton <paul.burton@mips.com>2018-06-24 09:26:02 -0700
commit972dc3b79f421b5ae553b1073708cbd0d4da4a91 (patch)
tree9380232cc760aff75133abb132881db5a410512d /arch/mips/include/asm/io.h
parent9c78ecaf7ba88818b45303365d05b5a3461e0f3b (diff)
MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefs
CONFIG_DMA_MAYBE_COHERENT already selects CONFIG_DMA_NONCOHERENT, so we can remove the extra conditions. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19529/ Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: David Daney <david.daney@cavium.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de> Cc: Huacai Chen <chenhc@lemote.com> Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org
Diffstat (limited to 'arch/mips/include/asm/io.h')
-rw-r--r--arch/mips/include/asm/io.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index cea8ad864b3f..a363d5fa281f 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -590,7 +590,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
*
* This API used to be exported; it now is for arch code internal use only.
*/
-#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
+#ifdef CONFIG_DMA_NONCOHERENT
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
@@ -609,7 +609,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
#define dma_cache_inv(start,size) \
do { (void) (start); (void) (size); } while (0)
-#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT */
/*
* Read a 32-bit register that requires a 64-bit read cycle on the bus.