diff options
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:44 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:23:38 +0200 |
| commit | 5e5b6527128cea50f12a7064bf61b130b3a2739a (patch) | |
| tree | 6dcaaf2a258785705bacc2447f4f639f575aa4c6 /arch/mips/include/asm/mach-ip22 | |
| parent | 802b83627f54d63d3d95d0285ec9a5d80be434c0 (diff) | |
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ip22')
| -rw-r--r-- | arch/mips/include/asm/mach-ip22/war.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h index 3424c1e8a24f..9154c54d428a 100644 --- a/arch/mips/include/asm/mach-ip22/war.h +++ b/arch/mips/include/asm/mach-ip22/war.h @@ -12,7 +12,6 @@ * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. */ -#define R4600_V1_HIT_CACHEOP_WAR 1 #define R4600_V2_HIT_CACHEOP_WAR 1 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 |