diff options
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:46 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:24:01 +0200 |
| commit | 142439b0520a239bc10cf6c87d7773644c5dfe04 (patch) | |
| tree | d5b96654d4cf4f3895a0f75d048f06944e20cb10 /arch/mips/include/asm/mach-ip30 | |
| parent | 44def3426e4ac5a2dbdb5c8304397f4daa38eb2f (diff) | |
MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ip30')
| -rw-r--r-- | arch/mips/include/asm/mach-ip30/war.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h index f887a0a53e18..acda1ee3fb62 100644 --- a/arch/mips/include/asm/mach-ip30/war.h +++ b/arch/mips/include/asm/mach-ip30/war.h @@ -7,8 +7,6 @@ #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0 #define ICACHE_REFILLS_WORKAROUND_WAR 0 #ifdef CONFIG_CPU_R10000 |