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authorSergio Paracuellos <sergio.paracuellos@gmail.com>2023-06-19 06:09:37 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2023-06-21 14:50:22 +0200
commit7cd1bb48885449a9323c7ff0f10012925e93b4e1 (patch)
tree64ccea3bab74f2cfeec0871bdfd971b8057291f2 /arch/mips/include/asm/mach-ralink/rt3883.h
parentdaf73c70f69386fb15960526772ef584a4efcaf2 (diff)
mips: ralink: rt3883: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ralink/rt3883.h')
-rw-r--r--arch/mips/include/asm/mach-ralink/rt3883.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
index ad25d5e8d2dc..4a835b178925 100644
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -92,14 +92,6 @@
#define RT3883_REVID_VER_ID_SHIFT 8
#define RT3883_REVID_ECO_ID_MASK 0x0f
-#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
-#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
-#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
-#define RT3883_SYSCFG0_CPUCLK_250 0x0
-#define RT3883_SYSCFG0_CPUCLK_384 0x1
-#define RT3883_SYSCFG0_CPUCLK_480 0x2
-#define RT3883_SYSCFG0_CPUCLK_500 0x3
-
#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)