diff options
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-08-24 18:32:47 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-07 22:24:09 +0200 |
| commit | 24a1c023f3ff3082fee9c019c17e6a34e2ddfe6b (patch) | |
| tree | 25ceb96a0bfd469da846b4140806161fe09fc806 /arch/mips/include/asm/mach-sibyte | |
| parent | 142439b0520a239bc10cf6c87d7773644c5dfe04 (diff) | |
MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-sibyte')
| -rw-r--r-- | arch/mips/include/asm/mach-sibyte/war.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h index 0e18f0753407..9e006fdcf38a 100644 --- a/arch/mips/include/asm/mach-sibyte/war.h +++ b/arch/mips/include/asm/mach-sibyte/war.h @@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void); #endif -#define TX49XX_ICACHE_INDEX_INV_WAR 0 #define ICACHE_REFILLS_WORKAROUND_WAR 0 #define R10000_LLSC_WAR 0 #define MIPS34K_MISSED_ITLB_WAR 0 |