diff options
| author | James Hogan <james.hogan@imgtec.com> | 2016-05-11 13:50:53 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:30:25 +0200 |
| commit | 30228c40f0c6f0a93910325f120904505a4c39cc (patch) | |
| tree | e94f33f75456f37efe79b1bcfb7b5359035dfbb1 /arch/mips/include/asm | |
| parent | f18bdfa191df3947879f93519ce4a4985e5f5fce (diff) | |
MIPS: Add perf counter feature
Add CPU feature for standard MIPS r2 performance counters, as determined
by the Config1.PC bit. Both perf_events and oprofile probe this bit, so
lets combine the probing and change both to use cpu_has_perf.
This will also be used for VZ support in KVM to know whether performance
counters exist which can be exposed to guests.
[ralf@linux-mips.org: resolve conflict.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Robert Richter <rric@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/13226/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 7962b257cc16..232b0377346a 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -454,4 +454,8 @@ # define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC) #endif +#ifndef cpu_has_perf +# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF) +#endif + #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index ddcb2abd44ba..3971a25e07a6 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -408,6 +408,7 @@ enum cpu_type_enum { #define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ #define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ #define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */ +#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */ /* * CPU ASE encodings |