diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2017-08-12 19:49:28 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-30 00:57:25 +0200 |
| commit | 2c981e325f0c18e24ce252f16f5018b9ee805212 (patch) | |
| tree | 95945f685403432d6221304e96ad61e84acb2a68 /arch/mips/include/asm | |
| parent | 93c5bba575cedbeb50c9e1b0676230139b0d1be1 (diff) | |
MIPS: CPC: Use common CPS accessor generation macros
Switch the MIPS Cluster Power Controller (CPC) accessor functions to be
generated by the new common Coherent Processing System (CPS) macros
shared with the Coherence Manager (CM).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17002/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mips-cpc.h | 63 |
1 files changed, 22 insertions, 41 deletions
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h index 8c519f9827a3..9de7addb59ba 100644 --- a/arch/mips/include/asm/mips-cpc.h +++ b/arch/mips/include/asm/mips-cpc.h @@ -13,6 +13,7 @@ #include <linux/io.h> #include <linux/types.h> +#include <asm/mips-cps.h> /* The base address of the CPC registers */ extern void __iomem *mips_cpc_base; @@ -61,54 +62,34 @@ static inline bool mips_cpc_present(void) #define MIPS_CPC_CLCB_OFS 0x2000 #define MIPS_CPC_COCB_OFS 0x4000 -/* Macros to ease the creation of register access functions */ -#define BUILD_CPC_R_(name, off) \ -static inline u32 *addr_cpc_##name(void) \ -{ \ - return (u32 *)(mips_cpc_base + (off)); \ -} \ - \ -static inline u32 read_cpc_##name(void) \ -{ \ - return __raw_readl(mips_cpc_base + (off)); \ -} - -#define BUILD_CPC__W(name, off) \ -static inline void write_cpc_##name(u32 value) \ -{ \ - __raw_writel(value, mips_cpc_base + (off)); \ -} - -#define BUILD_CPC_RW(name, off) \ - BUILD_CPC_R_(name, off) \ - BUILD_CPC__W(name, off) +#define CPC_ACCESSOR_RO(sz, off, name) \ + CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) -#define BUILD_CPC_Cx_R_(name, off) \ - BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \ - BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off)) +#define CPC_ACCESSOR_RW(sz, off, name) \ + CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) -#define BUILD_CPC_Cx__W(name, off) \ - BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \ - BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off)) +#define CPC_CX_ACCESSOR_RO(sz, off, name) \ + CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \ + CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name) -#define BUILD_CPC_Cx_RW(name, off) \ - BUILD_CPC_Cx_R_(name, off) \ - BUILD_CPC_Cx__W(name, off) +#define CPC_CX_ACCESSOR_RW(sz, off, name) \ + CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \ + CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name) /* GCB register accessor functions */ -BUILD_CPC_RW(access, MIPS_CPC_GCB_OFS + 0x00) -BUILD_CPC_RW(seqdel, MIPS_CPC_GCB_OFS + 0x08) -BUILD_CPC_RW(rail, MIPS_CPC_GCB_OFS + 0x10) -BUILD_CPC_RW(resetlen, MIPS_CPC_GCB_OFS + 0x18) -BUILD_CPC_R_(revision, MIPS_CPC_GCB_OFS + 0x20) +CPC_ACCESSOR_RW(32, 0x000, access) +CPC_ACCESSOR_RW(32, 0x008, seqdel) +CPC_ACCESSOR_RW(32, 0x010, rail) +CPC_ACCESSOR_RW(32, 0x018, resetlen) +CPC_ACCESSOR_RO(32, 0x020, revision) /* Core Local & Core Other accessor functions */ -BUILD_CPC_Cx_RW(cmd, 0x00) -BUILD_CPC_Cx_RW(stat_conf, 0x08) -BUILD_CPC_Cx_RW(other, 0x10) -BUILD_CPC_Cx_RW(vp_stop, 0x20) -BUILD_CPC_Cx_RW(vp_run, 0x28) -BUILD_CPC_Cx_RW(vp_running, 0x30) +CPC_CX_ACCESSOR_RW(32, 0x000, cmd) +CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf) +CPC_CX_ACCESSOR_RW(32, 0x010, other) +CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop) +CPC_CX_ACCESSOR_RW(32, 0x028, vp_run) +CPC_CX_ACCESSOR_RW(32, 0x030, vp_running) /* CPC_Cx_CMD register fields */ #define CPC_Cx_CMD_SHF 0 |