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authorMarkos Chandras <markos.chandras@imgtec.com>2015-07-09 10:40:46 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-08-26 15:23:14 +0200
commit391057d915f42d4942f0c65e7d55cec6662c8a54 (patch)
treed6c40a5a0fb2eb3cffea12ce12925c142689f12e /arch/mips/kernel/mips-cpc.c
parent038b0f536e45d85038428d2edc169f1f4089c36d (diff)
MIPS: CPC: Fix type for GCR CPC base reg for 64-bit
The GCR CPC base register is 64-bit on 64-bit processors so use the appropriate field. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10645/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/mips-cpc.c')
-rw-r--r--arch/mips/kernel/mips-cpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 11964501c4b0..e05aca41e087 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -23,7 +23,7 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
phys_addr_t __weak mips_cpc_phys_base(void)
{
- u32 cpc_base;
+ unsigned long cpc_base;
if (!mips_cm_present())
return 0;